Abstract: A semiconductor device structure and method are presented for increasing a breakdown voltage of a junction between a substrate of first conductivity type and a device region. The structure includes a region of second conductivity type in the substrate completely buried in the substrate below and separated from the device region. The region of second conductivity type is located a predetermined distance away from the device region. The distance is sufficient to permit a depletion region to form between the region of second conductivity type and the device region, when a first voltage is applied between the device region and the substrate. The distance also is determined to produce a radius of curvature of the depletion region, when a second voltage that is larger than the first voltage is applied between the device region and the substrate, that is larger than a radius of curvature of the depletion region about the device region that would be formed if the region of second conductivity type were not present.

Abstract: In a metal alloy formed by first and second metal members for a semiconductor device, the first metal member is composed of approximately 0.1 to 10 wt. percent Cu with the residual amount being substantially composed of Al, and the second metal member is composed of approximately 0.5 to 5 wt. percent with the residual amount being substantially composed of Au.

Abstract: A semiconductor device includes a silicon substrate, a first insulating film, a barrier film, a contact hole, a protective film, a barrier metal, and an interconnection metal. A semiconductor element is formed on the silicon substrate. The first insulating film is formed on the silicon substrate. The barrier film is formed on the first insulating film to prevent moisture from externally entering. The contact hole is formed through the barrier film and the insulating film to a depth at which the silicon substrate is exposed. The protective film is formed on the side surface of the contact hole to protect the first insulating film against etching which is performed to remove a spontaneous oxide film formed on a surface of the silicon substrate which is exposed on a bottom surface of the contact hole. The barrier metal is continuously formed on at least the side and bottom surfaces of the contact hole and serves as a buffer conductor.

Abstract: A semiconductor device having the base region surrounded by at least two continuous slots. The collector region is surrounded by at least one continuous slot formed as a continuation of one of the at least two continuous slots surrounding the base region. The portions of the slots that are over the buried layer extends beyond the surface of the buried layer and the portions of the slots not over the buried layer extends beyond the interface between the epitaxial layer and the substrate. The slots are filled with either polysilicon or tungsten. The base region terminates on the surface of the innermost slot surrounding the base region. The boundary of the base region terminates substantially perpendicular to the surface of the surrounding slot.

Abstract: A master slice semiconductor IC has a SOI substrate and a plurality of basic cells arranged in a matrix on the SOI substrate. The basic cell includes a two-input NAND gate and a diode forward biased between one of power supply lines and the NAND gate. The diode has a P-N junction extending between the top surface of a semiconductor layer and the insulator layer underlying the semiconductor layer. The diode reduces the supply voltage by the forward drop voltage thereof to reduce power consumption in the NAND gate, and the SOI structure of the basic cell prevents reduction of integration density and operational speed.

Abstract: A diode device for face down bonding use comprising: a semiconductor main body; a first region for forming an electrode, the region being exposed at a first surface of the semiconductor main body; a first electrode provided in the first region; a second region for forming another electrode, the second region being provided within the semiconductor main body; a third region conducting the second region to the first surface through the semiconductor main body; and a second electrode provided in the third region on the first surface.

Abstract: A double-crown shaped capacitor of a dynamic random access memory cell is disclosed. The capacitor includes a first crown-shaped conductive region formed over a semiconductor substrate, wherein the first crown-shaped conductive region communicates to the semiconductor substrate via a hole. The capacitor also includes a second crown-shaped conductive region formed over the semiconductor substrate, wherein the inner sidewall of the second crown-shaped conductive region abuts on the outer sidewall of said first crown-shaped conductive region. Finally, the capacitor includes a dielectric layer covering the first crown-shaped conductive region and the second crown-shaped conductive region, and includes a conductive layer (138) formed on the dielectric layer.

Abstract: A field oxide layer for a semiconductor device includes an upper portion of first thickness extending above the major surface of a semiconductor substrate, and a lower portion of second thickness extending below the major surface of the semiconductor substrate. The ratio of first thickness to second thickness is not less than 1 to 2.

Abstract: A fabrication process and transistor are described in which a transistor having decreased susceptibility to punchthrough and increased resistance to impurity diffusion is formed. One or more argon doped silicon epitaxial layers are formed superjacent a semiconductor substrate. In a preferred dual layer embodiment, a first argon doped silicon epilayer is grown over a substrate, and a second argon doped epilayer, preferably having an argon concentration less than that in the first epilayer, is formed over the first epilayer. A transistor is formed in an active region of a well having a channel laterally bounded by source/drain regions located exclusively in the second epilayer. The lighter argon doping of the second epilayer accommodates current flow in the channel while acting as a barrier to impurity outdiffusion and inhibiting punchthrough. The more heavily doped first epilayer serves primarily as a barrier to outdiffision of impurities from the bulk substrate.

Abstract: A double-crown shaped capacitor of a dynamic random access memory cell is disclosed. The capacitor includes a first crown-shaped doped polysiliocn region (118) formed over a semiconductor substrate (110), wherein the first crown-shaped doped polysiliocn region communicates to the semiconductor substrate. The capacitor also includes a second crown-shaped doped polysilicon region (128) formed over the semiconductor substrate, wherein the inner sidewall of the second crown-shaped doped polysilicon region abuts on the outer sidewall of aid first crown-shaped doped polysiliocn region. Finally, the capacitor includes a dielectric layer (136) covering the first crown-shaped doped polysiliocn region and the second crown-shaped doped polysilicon region, and includes a conductive layer (138) formed on the dielectric layer.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: A three dimensional capacitor structure particularly adapted for use as a memory cell capacitor of a DRAM is disclosed. The capacitor structure incorporates the substantially vertical (in relation to the substrate) sides of a plurality of spacers into the storage node capacitor to increase the total area of the storage node capacitor. In the described embodiments of the invention, a first spacer and a second spacer are formed next to the digit lines. The bottom storage node plate is formed on at least the first sides of the spacers to increase area of the storage node. The bottom storage node plate is also formed on the upper surface of the digit line. Additional spacers can also be added to further increase the area of the storage node. A dielectric layer is formed over the first capacitor plate and a second capacitor plate layer is formed over the dielectric layer to complete the structure.

Abstract: A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions.The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance.

Abstract: The amplification type solid-state imaging device of this invention includes amplification type photoelectric converting elements arranged in a matrix.

Abstract: A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated fin electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon

Abstract: A low contact resistance and low junction leakage metal interconnect contact structure for use with ICs. The contact structure includes an interconnect dielectric material layer on the surface of an IC semiconductor substrate. The interconnect dielectric material layer has a contact opening which extends to a predetermined region of the semiconductor substrate (e.g. a source region, drain region, or polysilicon gate layer). The contact structure also includes a cobalt (or nickel) silicide interface layer on the surface of the predetermined region that is aligned with the bottom of the contact opening, a cobalt (or nickel) adhesion layer on the sidewall surface of the contact opening, a refractory metal-based barrier layer on the metal adhesion layer and the metal silicide interface layer, and a conductive plug. Manufacturing process steps for such a contact structure include first providing a semiconductor substrate with at least one predetermined region (e.g.

Abstract: A thin film transistor and a method for fabricating the same are disclosed, in which an offset region is affected or biased by a gate voltage to increase on-current, thereby improving on/off characteristic of a device. A first semiconductor layer is formed on a substrate, and insulating layer patterns are formed at both ends of the first semiconductor layer. A second semiconductor layer is formed on the first semiconductor layer and the insulating layer patterns. A gate insulating film is formed on the first and second semiconductor layers and the insulating layer patterns, and an active layer formed on the gate insulating film.

Abstract: A photodetector design is disclosed for preventing an electrode from being broken. A recess portion is formed in a semiconductor substrate. A light absorbing layer is formed in the recess portion, and a buffer layer is formed on the light absorbing layer. A contact layer is formed on the buffer layer. The height of the light absorbing layer can be set to minimize the effect of a step caused by facet formation. An insulating layer is formed outside of a recess portion to project from a main surface of the substrate. The anode electrode is formed on the insulating layer and substantially outside of the recess and, as a result, the electrode is less likely to be broken.

Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.

Abstract: A MIM nonlinear device is provided having a large nonlinearity coefficient that represents the sharpness of the voltage-current characteristic. A liquid-crystal display panel may be manufactured using the device to exhibit high image-quality. A method for manufacturing such a MIM nonlinear device is also provided. A MIM nonlinear device may include a first conductive film, an insulating film and a second conductive film laminated on a substrate. The insulating film may contain water at a content gradient descending in the direction of the film thickness from the surface facing the second conductive film. The hydrogen spectrum that is derived from the water and obtained by a secondary ion-mass spectrography (SIMS) elemental analysis with the radiation of cesium primary ions exhibits a peak near a surface of the insulating film facing the second conductive film. Additionally, the thermal desorption spectroscopy of the insulating film has a peak derived from water in the insulating film within a range of 220.