Patents Examined by David C Spalla
  • Patent number: 11843031
    Abstract: A method is presented for forming a nanosheet device. The method includes forming nanosheets stacks over a substrate, the nanosheet stacks separated by shallow trench isolation (STI) regions, forming a first hardmask material over the nanosheet stacks, depositing a sacrificial gate, recessing the sacrificial gate such that recesses are defined adjacent the first hardmask material, wherein a top surface of the sacrificial gate is below a top surface of the first hardmask material, forming a second hardmask material in the recesses, defining a uniform gate length in both the first and second hardmask materials, and selectively trimming the first hardmask material such that a gate length over the nanosheet stacks is less than a gate length over the STI regions.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: December 12, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen Zhang, Kangguo Cheng, Wenyu Xu, Ruilong Xie
  • Patent number: 11843032
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [?1 0 0], [0 1 0], or [0 ?1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Siang Lan, Sathaiya Mahaveer Dhanyakumar, Tzer-Min Shen, Zhiqiang Wu
  • Patent number: 11842757
    Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsann Lin, Ji-Feng Ying, Chih-Chung Lai
  • Patent number: 11824102
    Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-An Lin, Kuo-Pi Tseng, Tzu-Chieh Su
  • Patent number: 11818961
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Vignesh Sundar, Yu-Jen Wang
  • Patent number: 11810948
    Abstract: An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
  • Patent number: 11805649
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: October 31, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Srinivas Pulugurtha, Johann Alsmeier, Yanli Zhang, James Kai
  • Patent number: 11804532
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first superlattice structure and a second superlattice structure over the substrate, a gate stack that surrounds a channel region of each of the first superlattice structures and the second superlattice structure, and source/drain structures on opposite sides of the gate stack contacting sidewalls of the first superlattice structure and the second superlattice structure. The second superlattice structure is disposed over the first superlattice structure. Each of the first superlattice structures and the second superlattice structure includes vertically stacked alternating first nanosheets of a first semiconductor material and second nanosheets of a second semiconductor material that is different from the first semiconductor material.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: October 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Cheng Liu, Kuei-Shu Chang Liao
  • Patent number: 11798945
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over the substrate. The semiconductor device further includes a first channel layer and a second channel layer and a first insulating structure interposing the first channel layer and the semiconductor layer and a second insulating structure interposing the first channel layer and the second channel layer. The semiconductor device further includes a gate stack abutting the first channel layer and the second channel layer, and the gate stack includes a first portion vertically sandwiched between the first channel layer and the semiconductor layer and a second portion vertically sandwiched between the first channel layer and the second channel layer.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 11791381
    Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soojin Jeong, Sunwook Kim, Junbeom Park, Seungmin Song
  • Patent number: 11791413
    Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: October 17, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shi-You Liu, Shih-Cheng Chen, Chia-Wei Chang, Chia-Ming Kuo, Tsai-Yu Wen, Yu-Ren Wang
  • Patent number: 11777033
    Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Cheng-Ting Chung, Chih-Hao Wang
  • Patent number: 11778892
    Abstract: A display device includes a substrate that includes a bending area, a display active layer disposed on the substrate and that displays an image, a polarization layer disposed on the display active layer, a protective layer that contacts an end of the polarization layer and covers the bending area of the substrate; and an adhesive layer disposed on a boundary between the polarization layer and the protective layer, the adhesive layer extends from the end of the polarization layer toward the bending area by an extension area to overlap a portion of the protective layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myoung-Ha Jeon, Ki Chang Lee
  • Patent number: 11769833
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: September 26, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Patent number: 11769813
    Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: September 26, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung Gil Kang, Dong Won Kim, Woo Seok Park, Keun Hwi Cho, Sung Gi Hur
  • Patent number: 11764265
    Abstract: A field effect transistor (FET) structure upon a substrate formed by forming a stack of nanosheets upon a semiconductor substrate, the stack including alternating layers of a compound semiconductor material and an elemental semiconductor material, forming a dummy gate structure upon the stack of nanosheets, recessing the stack of nanosheets in alignment with the dummy gate structure, recessing the compound semiconductor layers beyond the edges of the dummy gate, yielding indentations between adjacent semiconductor nanosheets. Further by filling the indentations with a bi-layer dielectric material, epitaxially growing source/drain regions adjacent to the nanosheet stack and bi-layer dielectric material, removing remaining portions of the compound semiconductor nanosheet layers, recessing the bi-layer dielectric material to expose an inner material layer, and forming gate structure layers in contact with first and second dielectric materials of the bi-layer dielectric material.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: September 19, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ruilong Xie, Julien Frougier, Juntao Li
  • Patent number: 11764261
    Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: September 19, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Pu Chiu, Tzung-Ying Lee, Dien-Yang Lu, Chun-Kai Chao, Chun-Mao Chiou
  • Patent number: 11764281
    Abstract: Fin-like field effect transistors (FinFETs) and methods of fabrication thereof are disclosed herein. The FinFETs disclosed herein have gate air spacers integrated into their gate structures. An exemplary transistor includes a fin and a gate structure disposed over the fin between a first epitaxial source/drain feature and a second epitaxial source/drain feature. The gate structure includes a gate electrode, a gate dielectric, and gate air spacers disposed between the gate dielectric and sidewalls of the gate electrode.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chien-Ning Yao, Bo-Feng Young, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11749743
    Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: September 5, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Tsuo-Wen Lu, Chia-Ming Kuo, Po-Jen Chuang, Chi-Mao Hsu
  • Patent number: 11735634
    Abstract: A method for forming heterogeneous complementary FETs using a compact stacked nanosheet process is disclosed. The method comprises forming a first nanosheet stack comprising two layers of a first channel material separated by a second sacrificial layer, forming over the first nanosheet stack an equivalent second nanosheet stack, wherein the first channel material is complementary to the second channel material. The method comprises further forming a first source region and a first drain region, thereby building a first FET, and forming over the first source region and the first drain region a second source region and a second drain region, thereby building a second FET, removing selectively sacrificial layers, and forming a gate stack comprising a gate-all-around structure around all channels.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Cezar Bogdan Zota, Clarissa Convertino, Kirsten Emilie Moselund