Abstract: A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.

Abstract: A method for forming a FinFET device is described. The method includes the following steps. A substrate is patterned to form fins. Dummy gate stack is formed on the substrate and over the fins, wherein the dummy gate stack may be formed by the following steps: a dummy layer is formed; a first etching step is performed on the dummy layer with a bromine containing etching gas to form a dummy strip; a second etching step is performed on the dummy strip with a chlorine containing etching gas to form the dummy gate stack. The dummy gate stack is replaced with a gate stack.

Abstract: One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring.

Abstract: Provided are a thin film transistor substrate and a display using the same. A thin film transistor substrate includes: a substrate, a first thin film transistor disposed on the substrate, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor disposed on the substrate, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer being disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer, and an etch-stopper layer disposed on the oxide semiconductor layer.

Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions.

Abstract: A stack package includes a second semiconductor die stacked on the first semiconductor die, a third semiconductor die disposed on the lifting supporter. The third semiconductor die vertically and partially overlapping with the second semiconductor die.

Abstract: A hermetic high-current electronic package includes a package body and a base plate hermetically coupled to the package body. A semiconductor device is thermally mounted to the base plate and has a high-current output. A high-current input/output (I/O) terminal is bonded to the high-current output of the semiconductor device by a strap terminal that is an integral high current heatsink terminal. The high-current I/O terminal passes through a hole formed in a sidewall of the package body. A ceramic seal surrounds the high-current I/O terminal and has a first surface hermetically bonded to an outer surface of the sidewall of the package body. A metal hermetic seal washer surrounds the high-current I/O terminal and is bonded to a second surface of the ceramic seal and bonded to a portion of the high-current I/O terminal that passes through the metal hermetic seal washer.

Abstract: A method for manufacturing a light emitting device includes: mounting a first light emitting element whose emission peak wavelength is in a range of 430 nm to 490 nm and a second light emitting element whose emission peak wavelength is in a range of 490 nm to 570 nm; and providing a light transmitting member including a red phosphor and at least one of a green phosphor of which a half width of an emission spectrum is not more than 45 nm and a blue phosphor of which a half width of an emission spectrum is not more than 60 nm. The step of providing the light transmitting member includes adding at least one of a predetermined amount of the green phosphor and a predetermined amount of the blue phosphor based on the emission peak wavelength of the second light emitting element.

Abstract: The present invention discloses a light-diffusion quantum dot nanostructure and an LED component having the same. The quantum dot nanostructure comprises an optical core, an organic ligand layer, a hydrophobic layer, an inorganic encapsulation layer, and a multi-layered water vapor barrier layer. In the present invention, the multi-layered water vapor barrier layer is particularly designed to an onion skin-like structure, so as to facilitate photoluminescence rays radiated from the optical core can emit out of the barrier layer via voids or pores of the onion skin-like structure, such that the uniformity of the spatial light output distribution of the LED component having the quantum dot nanostructures can be obviously enhanced. On the other hand, because the multi-layered water vapor barrier layer can also improve the dispersibility of the light-diffusion quantum dot nanostructures in a colloidal encapsulation of the LED component, the luminous intensity of the LED component is therefore increased.

Abstract: A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.

Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.

Abstract: A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.

Abstract: A package structure including a first semiconductor die, a second semiconductor die, a molding compound, a bridge structure, through insulator vias, an insulating encapsulant, conductive bumps, a redistribution layer and seed layers is provided. The molding compound encapsulates the first and second semiconductor die. The bridge structure is disposed on the molding compound and electrically connects the first semiconductor die with the second semiconductor die. The insulating encapsulant encapsulates the bridge structure and the through insulator vias. The conductive bumps are electrically connecting the first and second semiconductor dies to the bridge structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the bridge structure. The seed layers are respectively disposed in between the through insulator vias and the redistribution layer.

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.

Abstract: A field effect transistor including: a substrate, and at least gate electrode, a gate insulating film, a semiconductor layer, a protective layer for the semiconductor layer, a source electrode and a drain electrode provided on the substrate, wherein the source electrode and the drain electrode are connected with the semiconductor layer therebetween, the gate insulating film is between the gate electrode and the semiconductor layer, the protective layer is on at least one surface of the semiconductor layer, the semiconductor layer includes an oxide containing In atoms, Sn atoms and Zn atoms, the atomic composition ratio of Zn/(In+Sn+Zn) is 25 atom % or more and 75 atom % or less, and the atomic composition ratio of Sn/(In+Sn+Zn) is less than 50 atom %.

Abstract: A device for detecting electromagnetic radiation includes at least one thermal detector, placed on a substrate; an encapsulating structure forming a cavity housing the thermal detector, including at least one thin encapsulating layer; and at least one Fabry-Perot interference filter, formed by first and second semi-reflective mirrors that are separated from each other by a structured layer. A high-index layer of one of the semi-reflective mirrors is at least partially formed from the thin encapsulating layer.

Abstract: A semiconductor device includes a substrate and a gate dielectric layer on the substrate. The gate dielectric layer includes a single metal oxide layer. The semiconductor device includes a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line. The gate electrode stack includes a work function layer covering the sidewall and the bottom surface of the metal filling line. The gate electrode stack includes a capping layer in contact with the gate dielectric layer between sidewalls of the gate dielectric layer and sidewalls of the work function layer. The capping layer includes TaC and at least one of TiN or TaN. The gate electrode stack includes a barrier layer interposed between the capping layer and the sidewalls of the work function layer. The barrier layer comprises TaC and WN, and the barrier layer is in contact with the capping layer.

Abstract: An optoelectronic component includes a carrier, wherein a first optoelectronic semiconductor chip and a second optoelectronic semiconductor chip are arranged above a top side of the carrier, the optoelectronic semiconductor chips each include a top side, an underside situated opposite the top side, and side faces extending between the top side and the underside, the undersides of the optoelectronic semiconductor chips face the top side of the carrier, a first potting material is arranged above the top side of the carrier, the first potting material covering parts of the side faces of the first optoelectronic semiconductor chip, and a second potting material is arranged above the top side of the carrier, and the second potting material covering the first potting material.