Abstract: Aspects of the present disclosure disclose systems and methods for managing a level-two persistent cache. In various aspects, a solid-state drive is employed as a level-two cache to expand the capacity of existing caches. In particular, any data that is scheduled to be evicted or otherwise removed from a level-one cache is stored in the level-two cache with corresponding metadata in a manner that is quickly retrievable. The data contained within the level-two cache is managing using a cache list that manages and/or maintains data chunk entries added to the level-two cache based on a temporal access of the data chunk.

Abstract: Techniques for implementing a log-based storage scheme upon data storage devices are described herein. A data storage device is initialized by writing an identifying record. For each portion of data to be written to the drive, a first record including information regarding the anticipated nature of the portion of data is written prior to the data. The data is then written as a second record that includes at least the raw data as well as integrity verification information. A third record is stored following the second record, and includes an accounting and/or index of the data successfully written in the second record. On sequentially written devices, the information in the first stored record may be used to locate the third record, which in turn may be used to record data in the second record as well as the location of a first record of another portion of data.

Abstract: Techniques for storing data received by a data storage system involve performing inline compression on received data and storing resulting compressed data in segments of contiguous physical address space of a file system. Each segment spans multiple contiguous physical addresses and stores data of multiple contiguous logical addresses of a file. Each segment has an extent list that provides a location within that segment of the compressed data for each logical address.

Abstract: In various embodiments, a high-density solid-state storage unit includes a plurality of flash cards. Each flash card has a flash controller that incorporates one or more resources for facilitating compression and decompression operations. In one aspect, data reduction and data reconstruction operations can be performed in-line as data is stored to and retrieved from flash memory. In another aspect, data reduction and data reconstruction operations can be performed as a service. Any one of the plurality of flash cards can be used to provide data reduction or data reconstruction services on demand for any type of data, including system data, libraries, and firmware code.

Abstract: Aspects of the present disclosure involve a level two persistent cache. In various aspects, a solid-state drive is employed as a level-two cache to expand the capacity of existing caches. In particular, any data that is scheduled to be evicted or otherwise removed from a level-one cache is stored in the level-two cache with corresponding metadata in a manner that is quickly retrievable.

Abstract: Embodiments of the present disclosure describe a system and method for providing anti-replay protection. One embodiment describes a system comprising: a security device; and an anti-replay protected flash device comprising: a flash memory array; an authentication unit; and a secure memory, wherein the authentication unit and the secure memory are disposed in a security boundary.

Abstract: A semiconductor memory system or device includes a memory cell array and an address converter. The memory cell array includes a plurality of memory blocks, and there is at least one block that serves as a buffer. Each of the memory blocks includes at least one memory cell row. An address converting circuit along with a block copy circuit performs a block copy operation of copying data of a first memory block, which is a source block among the memory blocks, into a second block, which is a buffer or destination block, and maps a first logical address for accessing the first memory block onto a physical address designating the second block. The first memory block then can serve as a new destination block after the block copy operation of the first memory block is completed.

Abstract: In one general embodiment, a method includes receiving a request for a write operation to be performed in a tape drive, determining an expected transaction size of a next write operation, comparing the expected transaction size of the next write operation to each of a first transaction size threshold and a second transaction size threshold in response to receiving the request, determining an optimum a write procedure based at least in part on the comparison, and invoking the optimum write procedure in response to determining the optimum write procedure, wherein the first transaction size threshold is greater than the second transaction size threshold, and wherein the optimum write procedure is selected from the group consisting of: a backhitch write procedure, a same wrap backhitchless flush (SWBF) write procedure, and a recursively accumulating backhitchless flush (RABF) write procedure.

Abstract: Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section that is convertible in response to a section conversion instruction.

Abstract: An example method of managing memory includes identifying a first object of the first type to update, the first object being stored on a heap. The method also includes reading a first memory address stored in a second object of the second type and storing a copy of the first object at a second memory address. The first memory address is an initial memory address of the first object. The method further includes after the copy is stored, reading a third memory address stored in the second object. The third memory address is a current memory address of the first object. The method also includes determining whether the first memory address matches the third memory address, and when the first memory address is determined to match the third memory address, updating the first memory address stored in the second object with the second memory address.

Abstract: Systems and methods for maintaining cache coherency in a multiprocessor system with shared memory, including a write-data-invalid (WDI) state configured to reduce stalls during write operations. The WDI state is a dataless state with guaranteed write permissions. When a first processor of the multiprocessor system makes a write request for a first cache entry of a first cache, the WDI state associated with the first cache entry includes write permissions for the write to directly proceed to one or more higher levels of memory in the shared memory, such that delays associated with obtaining write permissions is reduced at the first cache. The WDI state is treated as an invalid state for a read request to the first cache entry by the first processor.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

Abstract: A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

Abstract: Some embodiments of the present invention include a method comprising: accessing units of network storage that encode state data of respective virtual machines, wherein the state data for respective ones of the virtual machines are stored in distinct ones of the network storage units such that the state data for more than one virtual machine are not commingled in any one of the network storage units.

Abstract: The present disclosure includes a method for transferring checkpoint information of a primary virtual machine from a primary host to a secondary host that includes, by the primary host, capturing checkpoint information from the primary virtual machine to a primary holding buffer on the primary host, generating a first number of partition state records from the checkpoint information, transmitting the first number of partition state records to the secondary host, receiving acknowledgements from the secondary host for a second number of partition state records, and tracking the second number of partition state records acknowledged by the secondary host.

Abstract: A method is provided for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory faster than the first memory and a third memory faster than the second memory. The method includes examining instructions being filled from the second memory to the third memory, extracting instruction information containing at least branch information; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that possibly be executed by the processor core based on one or more tracks from a plurality of instruction tracks from the first memory to the second memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second memory to the third memory before the processor core executes the instructions, such that the processor core fetches the instructions from the third memory.

Abstract: A method and system for dynamically managing memory in a computing environment using a control monitor. The control monitor (e.g., a virtual machine monitor or operating system kernel) includes a nomination module configured to collect memory statistics associated with at least one memory node. Based on the memory statistics, the control monitor detects one or more first pages accessed from a remote memory node at or above an access threshold. The nomination module nominates, via a communication to at least one of a scheduler module and a memory manager of the control monitor, the one or more first pages for migration to the remote memory node.

Abstract: A transactional memory system determines whether to pass control of a transaction to an about-to-run-out-of-resource handler. A processor of the transactional memory system determines information about an about-to-run-out-of-resource handler for transaction execution of a code region of a hardware transaction. The processor dynamically monitors an amount of available resource for the currently running code region of the hardware transaction. The processor detects that the amount of available resource for transactional execution of the hardware transaction is below a predetermined threshold level. The processor, based on the detecting, saves speculative state information of the hardware transaction, and executes the about-to-run-out-of-resource handler, the about-to-run-out-of-resource handler determining whether the hardware transaction is to be aborted or salvaged.

Abstract: Disclosed is an improved approach for managing updates to metadata for a virtualization environment. According to some embodiments, a compare and swap approach is taken to manage updates and to handle possible inconsistencies.

Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.