Patents Examined by David X Yi
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Patent number: 9740635Abstract: Computer-readable storage media, computing devices and methods associated with file cache management are discussed herein. In embodiments, a computing device may include a file cache and a file cache manager coupled with the file cache. The file cache manager may be configured to implement a context-aware eviction policy to identify a candidate file for deletion from the file cache, from a plurality of individual files contained within the file cache, based at least in part on file-level context information associated with the individual files. In embodiments, the file-level context information may include an indication of access recency and access frequency associated with the individual files. In such embodiments, identifying the candidate file for deletion from the file cache may be based, at least in part, on both the access recency and the access frequency of the individual files. Other embodiments may be described and/or claimed.Type: GrantFiled: March 12, 2015Date of Patent: August 22, 2017Assignee: Intel CorporationInventors: Ren Wang, Weishuang Zhao, Wei Shen, Michael P. Mesnier, Tsung-Yuan C. Tai, Mesut A. Ergin
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Patent number: 9740406Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and sorts data blocks of write data received in the random access memory of the data storage. A storage controller is communicatively coupled to the random access memory and the data storage and being configured to write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses. A method and processor-implemented process provide for sorting data blocks of write data received in random access memory of data storage. The method and processor-implemented process write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses.Type: GrantFiled: June 8, 2016Date of Patent: August 22, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Mark A. Gaertner, Brian Thomas Edgar
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Patent number: 9740565Abstract: A request is received to determine a consistent point of data stored in a file system of a storage system having storage units. In response to the request, a prime dependency list is retrieved from a first prime segment stored in a first storage unit, the prime dependency list including information identifying at least a second prime segment stored in a second storage unit. The first and second prime segments are identified by a first prime segment identifier (ID) and a second prime segment ID, respectively, which collectively identify a prime representing a first consistent view of the file system. The consistent point of data is determined based the prime segments listed in the prime dependency list, where the consistent point of data represents a file system state at a point in time for restoration of the file system back to a prior known state.Type: GrantFiled: July 10, 2015Date of Patent: August 22, 2017Assignee: EMC IP Holding Company LLCInventors: Soumyadeb Mitra, Windsor W. Hsu
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Patent number: 9733964Abstract: The subject matter of this specification can be implemented in, among other things, a method including receiving a request to create a live snapshot of a state of a virtual machine at a reference point-in-time. The virtual machine can have a memory and an original disk file. The method further includes creating, at the reference point-in-time, an overlay disk file to copy data from the original disk file. Data modifications after the reference point-in-time are performed in the original disk file but not in the overlay disk file. The method also includes creating a memory snapshot at the reference point-in-time. The method includes providing the live snapshot corresponding to the reference point-in-time. The live snapshot includes the overlay disk file and the memory snapshot.Type: GrantFiled: August 27, 2013Date of Patent: August 15, 2017Assignee: Red Hat, Inc.Inventor: Eric Blake
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Patent number: 9733831Abstract: In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.Type: GrantFiled: July 1, 2014Date of Patent: August 15, 2017Assignee: GLOBALFOUNDRIES INC.Inventor: Martin Ohmacht
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Patent number: 9734117Abstract: A data storage device may comprise a first non-volatile memory, configured to store storage System-On-Chip (SOC) data and protocol bridge data; a storage SOC comprising circuitry configured to control the data storage device and to, upon power-on, retrieve the storage SOC data from the first non-volatile memory and configure itself according to the retrieved storage SOC data; a bus coupled to the storage SOC; and a protocol bridge coupled to the bus and comprising circuitry configured to translate between a first and a second communication protocol and to, upon power-on, retrieve the protocol bridge data from the first non-volatile memory via the storage SOC and the bus and configure itself according to the retrieved protocol bridge data.Type: GrantFiled: January 26, 2015Date of Patent: August 15, 2017Assignee: Western Digital Technologies, Inc.Inventors: Timothy J. McCabe, John E. Maroney
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Patent number: 9734877Abstract: A method of operating a memory interface circuit involves selectively operating the memory interface in either a synchronous mode or an asynchronous mode, the synchronous mode controlled by a first clock signal; in asynchronous mode, controlling an address latch for latching an address of a memory location in a memory array, the address latch controlled by an asynchronous address control signal synchronized to a second clock signal that is faster than a third clock signal used to operate the memory array.Type: GrantFiled: December 6, 2011Date of Patent: August 15, 2017Assignee: Cypress Semiconductor CorporationInventors: Hamid Khodabandehlou, Syed Babar Raza
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Patent number: 9727492Abstract: Techniques for implementing a log-based storage scheme upon data storage devices are described herein. A data storage device is initialized by writing an identifying record. For each portion of data to be written to the drive, a first record including information regarding the anticipated nature of the portion of data is written prior to the data. The data is then written as a second record that includes at least the raw data as well as integrity verification information. A third record is stored following the second record, and includes an accounting and/or index of the data successfully written in the second record. On sequentially written devices, the information in the first stored record may be used to locate the third record, which in turn may be used to record data in the second record as well as the location of a first record of another portion of data.Type: GrantFiled: August 8, 2012Date of Patent: August 8, 2017Assignee: AMAZON TECHNOLOGIES, INC.Inventor: Kestutis Patiejunas
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Patent number: 9727260Abstract: Described herein are methods, systems and machine-readable media for migrating data between storage devices of a storage array. A metric is used to measure the optimality of candidate data migrations, the metric taking into account capacity balance and proper data striping. Candidate migrations are evaluated against the metric. The candidate migration that ranks as the best migration according to the metric may be carried out. This process of evaluating candidate migrations and carrying out the best candidate migration may be iterated until data is properly distributed among the storage devices of the storage array.Type: GrantFiled: July 24, 2015Date of Patent: August 8, 2017Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Brian Rowe, Bob Fozard
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Patent number: 9727483Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.Type: GrantFiled: June 1, 2015Date of Patent: August 8, 2017Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, Jay G. Heaslip, Kenneth A. Lauricella, Jeffrey A. Stuecheli
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Patent number: 9727252Abstract: Storage administrators would like to create snapshots of a storage array as frequently as possible, but too many concurrent snapshots can place an unnecessary load on the storage array. Described herein are techniques for scheduling snapshots on the storage array with the objective of minimizing the maximum number of simultaneous snapshots and/or temporally spacing apart snapshots from each other.Type: GrantFiled: April 6, 2015Date of Patent: August 8, 2017Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: George Costea, Eric Forgette
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Patent number: 9727479Abstract: Techniques are described for compressing cache pages from an LRU (Least-Recently-Used) queue so that data takes longer to age off and be removed from the cache. This increases the likelihood that data will be available within the cache upon subsequent re-access, reducing the need for costly disk accesses due to cache misses.Type: GrantFiled: September 30, 2014Date of Patent: August 8, 2017Assignee: EMC IP Holding Company LLCInventors: Philippe Armangau, Vasily Olegovich Zalunin, Rustem Rafikov, Christopher A. Seibel
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Patent number: 9727240Abstract: The invention relates to a data erasable method of memory in smart cards and smart cards thereof, which includes: when a CPU in the smart card determines a data erasable operation will be proceed in the specified memory of the smart card, cache the data to be written in a random memory cache of the specified memory; after sending a data erasable signal to the specified memory, control itself to enter a standby sleep mode. The data erasable signal is used to indicate the specified memory to process the data erasable operation by obtaining the data to be written from the random memory cache. Using the provided solution, the current of the machine card interface can be reduced when a data erasable is proceed in the specified memory of the smart card, thus abnormal conditions due to the high current of the machine card interface are avoided, and the power consumption is reduced at the same time, the standby time of the device which the smart card is in is improved.Type: GrantFiled: September 16, 2011Date of Patent: August 8, 2017Assignee: CHINA MOBILE COMMUNICATIONS CORPORATIONInventor: Lin Li
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Patent number: 9720840Abstract: Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set associative cache is configured to store instructions. The instruction fetch unit is in communication with the n-way set associative cache and is configured to power up a first way, where a first indication is associated with an instruction and indicates the way where a future instruction is located and where the future instruction is two or more instructions ahead of the current instruction.Type: GrantFiled: February 28, 2013Date of Patent: August 1, 2017Assignee: Imagination Technologies, LLCInventors: Ranganathan Sudhakar, Parthiv Pota
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Patent number: 9720606Abstract: Methods and structure for online migration of data in a storage system comprising a plurality of storage devices. The method comprises redefining a volume of a storage system mapped according to a first mapping structure by defining a second mapping structure. The method further comprises quiescing processing of host I/O requests directed to the volume and transitioning control of the volume from a first to a second volume manager so as to utilize the benefits of the second mapping structure. The method further comprises commencing processing of host I/O requests directed to the volume wherein the volume is mapped according to the second mapping structure. The method further comprises migrating, via the second volume manager, volume data to any of a plurality of storage devices of the system, online, without interrupting processing of host I/O requests directed to the volume. This migrates volume data without significant downtime or wasted space.Type: GrantFiled: October 26, 2010Date of Patent: August 1, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Keith W. Holt, John G. Logan, Kevin Kidney
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Patent number: 9720624Abstract: According to example embodiments, a method of controller a memory system using a controller includes receiving a first read count command, determining if a read count of a non-volatile memory in the memory system exceeds a threshold value, and performing a first reading operation on the non-volatile memory according to the first read command. If the read count of the non-volatile memory exceeds the threshold value, then addresses are selected to which a plurality of additive reading operation corresponding to the first read command will be performed, in a random neighbor selection operation. The plurality of additive reading operations for checking data of neighboring pages of the page for performing the reading operation are distributed and processed.Type: GrantFiled: January 22, 2015Date of Patent: August 1, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-kwon Moon, Kyung-ryun Kim, Dong-sub Kim, Kyung-ho Kim
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Patent number: 9720618Abstract: A method and system for synthesizing backup snapshots is discussed. IO's may be streamed from multiple locations, and placed in journal files. These journal files may thereafter be used to synthesize the backup snapshot.Type: GrantFiled: December 16, 2013Date of Patent: August 1, 2017Assignee: EMC IP Holding Company LLCInventors: Anestis Panidis, Assaf Natanzon, Saar Cohen
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Patent number: 9720830Abstract: Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.Type: GrantFiled: July 10, 2015Date of Patent: August 1, 2017Assignee: MACOM CONNECTIVITY SOLUTIONS, LLCInventor: Millind Mittal
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Patent number: 9715348Abstract: Presented herein are mass data storage systems, file system protocols, non-transitory machine readable devices, and methods for storing data blocks in data file systems. Methods for compressing snapshot data in a data file system are disclosed which include: loading a snapshot file with one or more data blocks, the snapshot representing a state of the data file system at a point in time; determining if at least one of the snapshot data blocks is less than a predetermined byte value; responsive to a snapshot data block having a size that is less than the predetermined byte value, identifying a packed block configured to store data chunks from plural distinct snapshots and having available sufficient storage space to store the snapshot data block; and adding to the packed block the snapshot data block and lost-write context information corresponding to the snapshot data block.Type: GrantFiled: September 9, 2015Date of Patent: July 25, 2017Assignee: NETAPP, INC.Inventors: Subramaniam Periyagaram, Ananthan Subramanian, Manish Katiyar
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Patent number: 9710397Abstract: Approaches to managing a composite, non-volatile data storage device are described. In one embodiment, a method for managing a composite storage device made up of fast non-volatile storage, such as a solid state device, and slower non-volatile storage, such as a traditional magnetic hard drive, can include maintaining a first data structure, which stores instances of recent access to each unit in a set of units in the fast non-volatile storage device, such as the SSD device and also maintaining a second data structure that indicates whether or not units in the slower storage device, such as the HDD, have been accessed at least a predetermined number of times. In one embodiment, the second data structure can be a queue of Bloom filters.Type: GrantFiled: September 6, 2012Date of Patent: July 18, 2017Assignee: Apple Inc.Inventors: Peter Macko, Wenguang Wang