Abstract: A position-sensing method and device for sensing the installation location (F1, . . . , Fi) of slave units (SE1, . . . , SEi) in an operating region (A1, . . . , Ai) of a system (A) comprising a number i of adjacent operating regions (A1, . . . , Ai) each having a slave unit, wherein the individual slave units (SE1, SEi) have a changeable operating function for achieving or changing the physical state in the operating region in question of the system, and wherein a respective sensor (S1, . . . , Si) is provided in each operating region in question in order to sense a measurement variable (T) proportional to the physical state in the operating region in question and an evaluating device is provided in order to determine, upon the activation or changing of the operating function of at least one slave unit (SE1, . . . , SEi), the installation location (F1, . . . , Fi) of said slave unit from the change in the measurement variables (T) over time.

Abstract: A connector includes a first pin which is configured to indicate an in-service signal, a second pin which is configured to indicate a power supply signal, a third pin which is configured to indicate a clock signal, and a fourth pin; the first pin which is configured to indicate a PCIe port signal; the first pin, the second pin, the third pin, and the fourth pin have an equal length; and the connector includes a first face and a second face, a limiting structure is arranged on the first face, the limiting structure is a boss or a groove, and the first pin is located in the middle of the first face.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: A baseboard management controller (BMC) system adaptable to support multiple computer platforms is disclosed. The BMC system has a BMC CPU chip including a processor executing firmware. The BMC CPU chip is coupled via an external bus to an interface chip. The interface chip includes input/output interfaces for different communication protocols to interface with components on a computer node.

Abstract: A communication port interface facilitates charging of a power source, such as a battery, while the power source remains coupled to a tool. The communication port interface also facilitates downloading of torque and/or angle log information from an electronic torque tool to an external device. Torque and/or angle preset job information may be entered in client software and uploaded from the external device to the electronic torque tool via the communication port interface. Additional information including real time clock information and wrench system parameters may be uploaded to the electronic torque tool via the communication port interface.

Abstract: A system includes a serial peripheral interface (SPI) buffer configured at an initial position. A low voltage differential signaling (LVDS) transceiver is configured above the SPI buffer. A capacitor couples the LVDS transceiver with the SPI buffer. The SPI buffer does not interfere with signals from the LVDS transceiver. The LVDS transceiver does not interfere with signals from the SPI buffer. An input/output (I/O) module receives a signal from the LVDS transceiver or the SPI buffer.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: The described techniques address deadlocking issues associated with interconnected hardware devices that share bus lines associated with a digital communication interface. A watchdog-based solution is described that may be implemented internally within the interconnected hardware devices or, alternatively, as an external component. The watchdog circuity may monitor a logic state of one or more internal connections of a hardware device and cause one or more portions of the hardware device to reset when a deadlock condition is detected using this internal monitoring.

Abstract: According to examples, an apparatus may include a processor that may access an assignment of a component connected to a downstream USB port, from among a plurality of downstream USB ports that are downstream of a display device, to a first physical host device from among a plurality of physical host devices connected to the display device via respective upstream USB ports. The apparatus may bind, based on the assignment, the downstream USB port to a first upstream USB port that connects the first physical host device to the display device. The binding may cause the component to be coupled to the first physical host device. The apparatus facilitates assignment of individual components connected to downstream USB ports to one of a plurality of upstream USB ports.

Abstract: An information handling system may include a host system including a processor and a management controller communicatively coupled to the processor and configured for out-of-band management of the host system. The information handling system may also include a Universal Serial Bus (USB) interface communicatively coupled to the management controller via a Peripheral Component Interconnect Enhanced (PCIe) card electro-mechanical (CEM) connector. The host system may implements a host-side subsystem configured to engage CEM terminations in response to a USB mode of the host-side subsystem being disabled and the host-side subsystem being in a main power state and selectively enable communication to and from a USB host of the host system via the PCIe CEM connector based on the USB mode of the host-side subsystem.

Abstract: Provided is a unit that causes transmission of smallest payload data to a communication interface to be in standby during a time period from a time, at which it is determined that a transmission time of smallest payload data exceeds a reference value during a control cycle, to a time at which the communication interface transmits the smallest payload data to be transmitted next after the most recent smallest payload data transmitted at the time.

Abstract: Disclosed is a hardware acceleration based automatic read control system and method for a serial peripheral interface (SPI). The automatic read control system includes an SPI module, an advanced peripheral bus (APB) module, an interrupt generation module, a direct memory access (DMA) controller, a state schedule control module, a register group module, a count signal generation module, a transmitted data buffer and a received data buffer; the state schedule control module, the register group module and the count signal generation module form a state machine system; and the state schedule control module controls automatic timed batch read of sensor data of the SPI according to configuration information of the register group module and counting and timing information of the count signal generation module.

Abstract: An I2C bus communication control method, device and system, and a readable storage medium. The method comprises: receiving configuration information of an I2C bus sent by an upper-layer application; analyzing the configuration information to obtain a plurality of polling parameters; writing the plurality of polling parameters into a polling table; and controlling the I2C bus, and executing a corresponding read-write operation according to the polling table. In the method, the read-write operation executed on the I2C bus is performed according to the polling table, thus an accurate communication condition of the I2C bus can be directly obtained on the basis of the polling table without accessing a bus state in a polling manner; congestion risks can be reduced, and the access efficiency of a single main device can also be achieved when a plurality of main devices exist.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: Apparatuses for controlling data transaction between master and slave devices are described. A master port connected to a master device can include a voltage regulator, a bridging circuit connected to a network element, and a redriver circuit. In response to a data transaction corresponding to a first type of data transaction, the master port can activate the voltage regulator and deactivate the redriver circuit to support a first operation mode causing the master device to perform the data transaction with a slave device via the network element. In response to the data transaction corresponding to a second type of data transaction, the master port can deactivate the voltage regulator and activate the redriver circuit to support a second operation mode causing the master port to disconnect from a slave port connected to the slave device and the data transaction is fulfilled by a circuit connected to the slave device.

Abstract: A system for data transmission between two devices, including an output device having a binary output interface and a first field device having a binary input interface connected in a signal-transmitting manner to the binary output interface via a unidirectional connection. The output device includes a signal processing module which is set up to convert a data set to be transmitted to a binary, discrete-time signal in accordance with a serial protocol. The first field device includes a signal processing module which is set up to convert the received binary, discrete-time signal to the data set in accordance with the serial protocol. The invention further relates to a valve system.

Abstract: [Overview] [Problem to be Solved] To provide a communication device and a communication system that each enable transmission of a command and data of I3C in a protocol different from the I3C. [Solution] A communication device according to a first aspect of the present disclosure includes: an I3C device section that generates a command and data of I3C; and a communication device section that transmits the command and data of the I3C to another communication device via a bus by using a payload in a protocol different from the I3C.

Abstract: The disclosure provides a method and an apparatus for realizing USB communication; the method includes: step S1, when receiving a command sent by a host computer, a device determines a type of the command and returns enumerated general information of the device to the host computer if the command is an enumerating command, go back to step S1; if the command is a setting report command, the device acquires response data according to the setting report command and stores the response data, go back to step S1; if the command is a getting report command, the device selects a corresponding report size according to a size of current response data, acquires a second report identification corresponding to the report size, generates return data according to the acquired second report identification and the current response data and sends the return data to the host computer, go back to step S1.

Abstract: Provided are a method and apparatus for multi-bus device fused access. The method includes: receiving, by a bus, an instruction for accessing a fused node of a device, which instruction containing a matching word, an initial address, and an offset; performing matching according to the matching word and activating a fused drive; acquiring, by the fused drive, the initial address and the offset from the instruction on the bus respectively; computing an address of a first bus of the device according to the initial address, and computing an address of a second bus of the device according to the initial address and the offset; and accessing the device according to the address of the first bus so as to acquire first information, and accessing the device according to the address of the second bus so as to acquire second information.

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.