Abstract: A computer-implemented method according to one embodiment includes receiving, at a peripheral device via an in-band interface, a predetermined command; determining, by the peripheral device, a predetermined identifier within the predetermined command; and implementing, by the peripheral device, parameter data associated with the predetermined identifier, in response to the determining.

Abstract: A system for determine presence or quality of an external timing device is provided. The system may include a circuit (e.g., in a field-programmable gate array (FPGA)) having an input, an oscillator, an edge detector, a bit counter, and a calculator element. In some examples, the input may receive an input signal under test. The oscillator may advance a timer at a known rate to facilitate generation of clock samples for the input signal under test. The edge detector may measure edges of the input signal under test based on the clock samples. The circuit may include at least one bit counter to store a count associated with the measured edges for a shorter interval timer period and a longer interval timer period. The calculator element may determine presence or quality of an external timing device based on the count.

Abstract: A communication system according to the present disclosure includes a first communication unit that includes a first terminal, a transmission circuit configured to transmit a clock signal via the first terminal, a first resistor inserted into a path between the first terminal and a power supply, a first switch configured to couple the power supply and the first terminal to each other by being turned on, and a first controller configured to control an operation of the first switch, and a second communication unit that includes a second terminal coupled to the first terminal of the first communication unit via a first wiring line, a reception circuit configured to receive the clock signal via the second terminal, a power storage device, a second switch configured to couple the second terminal and the power storage device to each other by being turned on, and a second controller configured to control an operation of the second switch, the second communication unit being configured to operate by supply of a volta

Abstract: Differing widths of retimers are developed using differing numbers of individual retimer elements combined together. To maintain synchronous operation, various signals are provided between the individual retimer elements to allow synchronization of the various operations. A first signal is a wired-OR signal that is used for event and operation synchronization. A second set of signals form a serial bus used to transfer proper state information and operation correction data from a master retimer element to slave timer elements. The combination of the wired-OR signal and the serial bus allow the various state machines and operations inside each retimer element to be synchronized, so that the entire width of the link is properly synchronized.

Abstract: According to one embodiment, an electronic apparatus includes a receiver and a transmitter. The receiver receives a video signal from an external electronic apparatus through a cable conforming to a High-Definition Multimedia Interface (HDMI) standard. The receiver receives, from the external electronic apparatus through the cable, information for transferring a signal using a function of Audio Return Channel (ARC) or enhanced Audio Return Channel (eARC) of the HDMI standard. The transmitter transmits a position information signal or an audio signal to the external electronic apparatus through the cable, in accordance with the received information.

Abstract: An interface control circuit includes an interface wrapper, a logic circuit, a multiplexer and a command decoder. The interface wrapper transceives a plurality of first signals in a first interface, converts the first signals to a plurality of second signals in a second interface, and generates at least one first command signal according to the first signals. The logic circuit receives the second signals, and generates a second command signal according to the second signals. The multiplexer receives the first command signal and the second command signal, and generates a third command signal according to the first command signal and the second command signal. The command decoder receives the third command signal and generates the decoded command according to the third command signal.

Abstract: An information processing system includes a control unit, a peripheral device including a first register, a second register, and an initialization flag circuit, in which the initialization flag circuit is configured to output a high level signal when the information processing system is started and is configured to output a low level signal in a case where data indicating a low level is written into the second register, the low level signal being the same level as the low level, and in which the control unit is configured to write initial setting data for initializing the peripheral device into the first register in a case where the control unit determines that an output signal from the initialization flag circuit is a high level and is configured to write data indicating a low level into the second register, the low level indicating that writing of the initial setting data is completed.

Abstract: The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.

Abstract: Disclosed embodiments include a serial buffer device comprising first and second serial input/output (I/O) ports, first and second comparators, and a multiplexer having a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. There is also a transistor, a third comparator having first and second inputs and an output, wherein the first input is coupled to the second serial I/O port, the second input is coupled to a third reference voltage source, and the output is coupled to the control terminal of the multiplexer. Additionally, the embodiment includes an impedance controlled driver circuit having an input and an output, wherein the input is coupled to the output of the third comparator and the output is coupled to the first serial I/O port.

Abstract: A method and apparatus for data transfer in a data processing network uses both ordered and optimized write requests. A first write request is received at a first node of the data processing network is directed to a first address and has a first stream identifier. The first node determines if any previous write request with the same first stream identifier is pending. When a previous write request is pending, a request for an ordered write is sent to a Home Node of the data processing network associated with the first address. When no previous write request to the first stream identifier is pending, a request for an optimized write is sent to the Home Node. The Home Node and first node are configured to complete a sequence of ordered write requests before the associated data is made available to other elements of the data processing network.

Abstract: Described are mechanisms and methods to facilitate power saving in Type-C connectors. Some embodiments may comprise an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port, a first circuitry, and a second circuitry. The first circuitry may be operable to place toggled values on the CC signal path. The second circuitry may be operable to couple the ground signal path to a detection signal path. The placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device, and may be disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

Abstract: This control device comprises a communication unit, one or more functional units, and communication lines that connect the communication unit and the one or more functional units and are independent of each other. The communication unit is configured to execute a first task of sending out, with a first cycle, a first communication frame for executing transmission of data collected by the functional unit to the communication unit and/or transmission of data held by the communication unit to the functional unit via a first communication line among the communication lines, and a second task of sending out, with a second cycle different from the first cycle, a second communication frame for executing transmission of the data collected by the functional unit to the communication unit and/or transmission of the data held by the communication unit to the functional unit via a second communication line among the communication lines.

Abstract: A storage device including a memory array and a peripheral logic circuit is provided. The memory array includes a plurality of banks and a data path. The peripheral logic circuit operates in a copy mode or a normal mode according to a mode-switch command. In the copy mode, the peripheral logic circuit directs a first bank to provide specific data to the data path and directs a second bank to receive specific data from the data path.

Abstract: Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.

Abstract: An IHS (Information Handling System) may support a variety of types of peripheral devices that may each be customized for operation by a specific user. Embodiments provide management of peripherals devices based on the context of the use of the IHS by the specific user. Upon detecting a login by a user, a plurality of peripheral device settings associated with that user are retrieved from a remote management service. A context of use of the IHS is determined based in part on the physical configuration of the IHS, applications that are currently in use, and other indicators of a mode of operation of the IHS. Based on the context of use and the peripherals coupled to the IHS, settings are selected from the user's retrieved peripheral device settings. The peripheral devices are configured based on the selected settings.

Abstract: An electronic device comprising a USB port and a PCB is provided. A first cabling layer of the PCB has a first floating area and a line outside the first floating area, an insulation medium is between the first floating area and the line, a second cabling layer of the PCB is adjacent to the first cabling layer and has a first metal area, an orthographic projection of the first floating area on the second cabling layer and the first metal area have an overlapping area, and the first floating area is not connected to the first metal area; and a metal housing of the USB port has a plurality of fixed contacts fastened to the PCB and not connected to a ground of the PCB, the contacts include a first fixed contact connected to the first floating area and not connected to the first metal area.

Abstract: An electronic apparatus, comprising: data and charging port, direct current charging port, data interface, power switch, charging management module, main processor, video receiver, and video processing module. The power switch detects whether data and charging port or direct current charging port is transferring electrical energy, and enables, according to detection result, conduction between the data and charging port or the direct current charging port and the charging management module. The charging management module employs, after becoming in conduction with the data and charging port or the direct current charging port, the data and charging port or the direct current charging port to charge battery. The main processor controls the video receiver to detect whether the data and charging port or the data interface is transmitting video data, and receives, according to detection result, one video data flow and sends the same to the video processing module for processing.

Abstract: A communication system capable of shortening a setting time of an ID and reducing an incorrect setting is provided. A writing device sequentially transmits an ID of a plurality of slave devices after transmitting of the ID of a master device. The master device includes a plurality of semiconductor relays provided for each of the plurality of master slave devices for supplying power to the corresponding slave devices. The master device receives the ID of the master device from the writing device, and sets it as its own ID. The master device, every time the ID of the plurality of slave devices is received from the writing device after setting the ID of its own, turns on the semiconductor relays in order. The plurality of slave devices sets the ID received after power supply as its own ID.

Abstract: A control arrangement for a coffee machine is provided and comprises a central unit having a main control unit and a plurality of peripheral units/components. Each peripheral unit/component is connected to the central unit by means of a “smart” connector, which is coded and which can provide information relating to the unit/component connected thereto to the main control unit. In order to allow information to be transferred, the central unit comprises a master communication device, each peripheral unit/component is provided with a slave communication device, and a communication line is provided for connecting the master communication device to the slave communication devices. The transferred information is unambiguously associated to the unit/component and may comprise counters, historical information, performance data and the like.