Abstract: The wireless module according to the present invention includes a wireless IC chip for processing transmission/reception signals, a substrate on which the wireless IC chip is mounted, an antenna provided on the substrate, and a plurality of terminals extending off from the substrate in an in-plane direction of the substrate.

Abstract: A semiconductor device has a semiconductor chip adhesively bonded to a die pad. An area having large irregularities is formed on an upper side surface of the semiconductor chip to be covered by an encapsulating resin, and an area having small irregularities is formed on a lower side surface of the semiconductor chip, thereby improving adhesive strength between the semiconductor chip and the encapsulating resin and preventing penetration of moisture from outside.

Abstract: A cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the method comprises attaching a metal heat sink to a leadframe using an intermediate structure that is thermally conductive and electrically insulating; molding a plastic body around the heat sink and exposed leads of the leadframe to form a cavity, with partially and selectively exposed lead top surfaces, heat sink top surface, and heat sink bottom surface; attaching a semiconductor device die within cavity on to the exposed top surface of the heat sink using a thermal conductive material; wire bonding respective wire bond pads of the semiconductor device die to the exposed lead top surfaces and to the heat sink for grounding; and attaching a lid to the plastic molded body to protect the wire bonded device within cavity.

Abstract: A chip-stacking apparatus for stacking a chip on a substrate is provided. The chip-stacking apparatus includes a substrate support configured to carry the substrate and a transport device configured to dispose a chip to the substrate. The transport device includes a bond head including a bond base and an attaching element disposed on the bond base and configured to allow the chip to be attached thereon. The center area of the attaching element is higher than an edge area of the attaching element relative to the bond base.

Abstract: A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area and a second area that is provided independently from the first area, the first area including a first circuit formed in the first area, and the second area including a second circuit formed in the second area.

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the

Abstract: A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

Abstract: A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

Abstract: An assembly can include a first microelectronic package and a circuit structure comprising a plurality of dielectric layers and electrically conductive features thereon. The first package can include a substrate having a plurality of first contacts at a first or second surface thereof and a plurality of second contacts at the first surface thereof, and a first microelectronic element having a plurality of element contacts at a front surface thereof. The first contacts can be electrically coupled with the element contacts of the first microelectronic element. The electrically conductive features of the first circuit structure can include a plurality of bumps at the first surface of the circuit structure facing the second contacts of the substrate and joined thereto, a plurality of circuit structure contacts at a second surface of the circuit structure, and a plurality of traces coupling at least some of the bumps with the circuit structure contacts.

Abstract: A method includes mounting a window substrate to a carrier tape. The window substrate has a window extending between an upper surface of the window substrate and a lower surface of the window substrate, the carrier tape sealing the window at the lower surface. Bond pads on an active surface of a MEMS die are flip chip mounted to terminals on the upper surface of the window substrate, a MEMS active area of the MEMS die being aligned with the window of the window substrate. A magnet is mounted to an inactive surface of the MEMS die.

Abstract: Provided are a printed circuit board which can be used as a substrate for a package, a method of manufacturing the printed circuit board, and a semiconductor package using the printed circuit board, the printed circuit board including: a first substrate having a first mounting area for mounting a package substrate and a second mounting area for mounting a semiconductor element; a single layer or multi-layered circuit pattern of the first substrate; and a post bump connected to the circuit pattern, provided on an external insulating layer of the first mounting area, and having a concave upper surface.

Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.

Abstract: Provided is a heat conductive silicone composition disposed between a heat generating electronic component and a member for dispersing heat, wherein the heat conductive silicone composition contains (A) an organopolysiloxane having at least two alkenyl groups in one molecule and having a dynamic viscosity at 25° C. of 10 to 100,000 mm2/s, (B) a hydrolyzable dimethylpolysiloxane having three functional groups at one end expressed by formula (1), (C) a heat conductive filler having a heat conductivity of 10 W/m° C. or higher, (D) an organohydrogenpolysiloxane expressed by formula (2), (E) an organohydrogenpolysiloxane containing a hydrogen directly bonded to at least two silicon atoms in one molecule other than component (D), and (F) a catalyst selected from the group consisting of platinum and platinum compounds.

Abstract: A semiconductor device includes a lead frame having terminals, a semiconductor chip electrically coupled to the terminals, and a resin part configured to encapsulate the semiconductor chip such as to expose part of the terminals, wherein a given one of the terminals includes a first lead and a second lead welded together such that an upper face of the first lead is placed against a lower face of the second lead, wherein the lower face of the second lead extends further than the upper face of the first lead toward the semiconductor chip in a longitudinal direction of the terminal, and also extends further sideways than the upper face of the first lead in a transverse direction of the terminal, and wherein an area of the lower face of the second lead is covered with the resin part, the area extending further than the upper face of the first lead.

Abstract: A microphone system has a package forming an interior chamber, and a MEMS microphone secured within the interior chamber. The package forms an aperture for permitting acoustic access to the interior of the chamber and thus, the MEMS microphone. The system also has two dies; namely, the system has a primary circuit die within the interior chamber, and an integrated passive device die electrically connected with the primary circuit die. The primary circuit die is electrically connected with the MEMS microphone and has at least one active circuit element.

Abstract: A semiconductor device uses a lead frame, in which an outer lead is electrically connected to an inner lead suspension lead via an inner lead. An encapsulating resin covers the inner lead and part of the outer lead, and a plated film is formed on an outer lead cut surface so that a solder layer is easily formed on all surfaces of the outer lead extending from the encapsulating resin. The inner lead suspension lead includes a narrowed portion that is smaller in cross-sectional area than other portions of the inner lead suspension lead to suppress impact forces generated when the inner lead suspension lead is cut.

Abstract: Compositions containing an adhesive material, a release additive and a copper passivation agent are suitable for temporarily bonding two surfaces, such as a semiconductor substrate active side and a carrier substrate. These compositions are useful in the manufacture of electronic devices where a temporary bonding of a component to a substrate having a copper surface is desired.

Abstract: A semiconductor device of the present invention includes: a first substrate (1) on which a power semiconductor element (2) is mounted; a heat-dissipating plate (12); an insulating layer (11) disposed between the first substrate (1) and the heat-dissipating plate (12); and molding resin (4) that molds the first substrate (1), the heat-dissipating plate (12), and the insulating layer (11). The heat-dissipating plate (12) has a first surface opposite to the insulating layer (12), the first surface being exposed from the molding resin (4). The insulating layer (11) has a curved area (11a) that is curved to the first surface and an end that is located in the molding resin (4).

Abstract: A package structure includes a substrate having a first bond pad layer. A silicon bridge layer having one or more redistribution layers therein. The silicon bridge layer has a second bond pad, and the silicon bridge layer is attached to the substrate by an adhesive layer. A first die is coupled to the substrate and the silicon bridge layer. A second die is coupled to the silicon bridge layer, wherein the first die and the second die communicate with one another by way of the one or more redistribution layers. Power and/or ground connectors are coupled to the first bond pad and the second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second die.

Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.