Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract: A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly.

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device has a substrate having a first surface and a second surface opposite the first surface. Also, the substrate has a first hole. A plurality of leads is disposed over the first surface of the substrate and a die paddle is disposed in the first hole. Additionally, an encapsulant is disposed on the die paddle and the plurality of leads.

Abstract: A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.

Abstract: Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate.

Abstract: Reliability is improved by improving adhesiveness, crack resistance, and moisture resistance of a metal member-resin jointed body by enhancing adhesiveness between the metal member and the resin. A jointed body of a metal member and a resin including: an intermediate layer and a silane coupling agent layer formed on the metal member at an interface between the metal member and the resin, wherein the silane coupling agent layer and the resin are contacted; the intermediate layer is any one of an oxide layer of the metal, a chelating agent layer, a composite layer made of the oxide layer and the chelating agent layer, and a mixed layer made of the oxide and the chelating agent; and the intermediate layer has an electrically non-insulating characteristic, and a method of manufacturing the same.

Abstract: A semiconductor assembly comprises a package, which in turn comprises at least one substrate, a first die stacked onto the substrate, at least one further die stacked onto the first die, at least one heat spreader in the package, and TSV:s extending through the stacked dies. The ends of the TSV:s are exposed at the further die.

Abstract: The wireless module according to the present invention includes a wireless IC chip for processing transmission/reception signals, a substrate on which the wireless IC chip is mounted, an antenna provided on the substrate, and a plurality of terminals extending off from the substrate in an in-plane direction of the substrate.

Abstract: A semiconductor device includes at least one semiconductor chip, a first lead, and a second lead. The first lead includes a first portion connected to the semiconductor chip via a first wiring. The second lead includes a first portion connected to the semiconductor chip via a second wiring. The first portion of the first lead and the first portion of the second lead extend along a first direction. The first portion of the first lead is disposed so as to oppose the first portion of the second lead. The semiconductor chip is disposed between the first portion of the first lead and the first portion of the second lead.

Abstract: A direct multiple substrate die assembly can include a first and a second substrate, wherein each substrate can include at least one interlocking edge feature. An electrical interconnection area can be formed adjacent to or within the interlocking edge feature on each substrate and can be configured to couple one or more electrical signals between the substrates. In one embodiment, the interlocking edge feature can include one or more keying features that can enable accurate alignment between the substrates. In yet another embodiment, the direct multiple substrate die assembly can be mounted out of plane with respect to a supporting substrate.

Abstract: A semiconductor device and its fabrication method are provided. A first dielectric layer is provided to cover a substrate. The first dielectric layer contains a plurality of first conductive layers. A portion of each first conductive layer is removed to form a plurality of first openings in the first dielectric layer. A second dielectric layer is formed in each first opening. A third dielectric layer having second-openings are formed on the first dielectric layer and on the second dielectric layers. Each second-opening exposes at least two adjacent second dielectric layers. Second dielectric layers exposed by a first second-opening are removed to form third openings to expose corresponding first conductive layers. Second conductive layers are formed in the third opening and the second-openings including the first second-opening. Stable electrical interconnections with high quality electrical isolations can be provided.

Abstract: In an embodiment, there is provided a packaging arrangement comprising a substrate; a multi-memory die coupled to the substrate, wherein the multi-memory die comprises multiple individual memory dies, and each of the multiple individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies, and the multi-memory die is created by singulating the wafer of semiconductor material into memory dies, where at least one of the memory dies is the multi-memory die that includes the multiple individual memory dies that are still physically connected together; and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate.

Abstract: A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having a bottom surface located at a first level; and at least one electrical connector disposed at the first side of the encapsulating structure outside the recess, wherein a surface of the at least one electrical connector facing the encapsulating structure may be disposed at a second level different from the first level.

Abstract: The invention relates to a formulation which contains at least one silane and at least one carbon polymer in a solvent, and to the production of a silicon layer on a substrate which is coated with such a formulation.

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract: An ultraviolet semiconductor light-emitting element comprises a light-emitting layer which is arranged between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, an n-electrode that is in contact with the n-type nitride semiconductor layer, and a p-electrode that is in contact with the p-type nitride semiconductor layer. The p-type nitride semiconductor layer is provided with a p-type contact layer that has a band gap smaller than that of the light-emitting layer and is in ohmic contact with the p-electrode. A depressed part is formed in a reverse side surface of a surface of the p-type nitride semiconductor layer that faces the light-emitting layer so as to avoid a formation region on which the p-electrode is formed. A reflective film that reflects ultraviolet light emitted from the light-emitting layer is formed on an inner bottom surface of the depressed part.

Abstract: Disclosed is a semiconductor sensor device, including a substrate, a sensor element mounted on the substrate, a hollow member configured to surround a periphery of the sensor element, a sealing material configured to fill in the hollow member and cover the sensor element, and a recess formed on the substrate, the recess being configured to position the hollow member.

Abstract: An electronic component built-in substrate, includes a lower wiring substrate, an electronic component mounted on the lower wiring substrate, an intermediate wiring substrate including an opening portion in which the electronic component is mounted, and arranged in a periphery of the electronic component, and connected to the lower wiring substrate via a first conductive ball, an upper wiring substrate arranged over the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second conductive ball, and a resin filled into respective areas between the lower wiring substrate, the intermediate wiring substrate, and the upper wiring substrate, and sealing the electronic component, wherein the first conductive ball and the second conductive ball are arranged in displaced positions mutually.

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.