Patents Examined by Duane Kobayashi
  • Patent number: 5351272
    Abstract: The present invention discloses an improved electrical communication apparatus which communicates high speed data/information over existing AC wiring, provides a phase linear environment for electrical transmission and reception of information on electrical wiring and provides a means for simultaneous transmission and reception of multiple data/information streams via the use of dielectric core couplers. This invention provides a means for linking 2 or more microprocessor based or electronic devices via conventional electric lines such as power lines, building wiring, twisted pair, coaxial cable or other wiring.
    Type: Grant
    Filed: May 18, 1992
    Date of Patent: September 27, 1994
    Inventor: Karoly C. Abraham
  • Patent number: 5349612
    Abstract: A self calibrated time delay circuit including a plurality of serially connected unit delay cells each having an output tap which is selectable, a registration means for simultaneously determining the status of each output node of each of the unit delay cells, combinatorial and sequential logic units for analyzing said registration means and sending error correction commands to an up/down controller, said up down controller providing a command code for controlling the delay of each said unit delay by selecting which tap is output from said unit delay cell.
    Type: Grant
    Filed: June 19, 1992
    Date of Patent: September 20, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bin Guo, James J. Kubinec
  • Patent number: 5349611
    Abstract: Input data symbols are written in a write buffer then to a sync adder, which appends a pseudo randomly (PN) generated sync bit to the MSB position of a four-symbol sync word data field, to generate a sync word. Sync words may or may not be randomized and sent to a receiver whereafter synchronization is recovered and perhaps de-randomized symbols are written into particular positions of an ECC block in a read buffer which are derivable from the PN sequence. The ECC block is a data array having multi-bit sync words making up its rows and the bit positions of the sync words making up its columns. Synchronization recovery apparatus conceptually looks at each bit position across a row and in a top-to-bottom direction down each of the columns to locate that column which contains the appended PN sequence. Sync recovery involves the receiver re-generating the same PN sequence that was generated at the transmitter.
    Type: Grant
    Filed: January 13, 1993
    Date of Patent: September 20, 1994
    Assignee: Ampex Systems Corporation
    Inventor: George R. Varian
  • Patent number: 5347539
    Abstract: A two wire modem selects a carrier frequency in a baud rate from a predetermined plurality of carrier frequencies and baud rates to communicate with another modem over a communication media in a full duplex mode based on signal and echo characteristics of the communication media estimated by the modem. In addition, the processes of estimating channel characteristics and estimating range are combined in a common start up procedure comprising a plurality of successive time segments for a call modem to communicate with an answer modem over a communication media. Still further, a method is provided for switching from a primary communication media connection to a secondary connection of a data communications network for communication by first and second modems coupled to the network. More specifically, when a failure is detected in the primary connection, the secondary connection is qualified before switching thereto.
    Type: Grant
    Filed: January 15, 1993
    Date of Patent: September 13, 1994
    Assignee: Codex Corporation
    Inventors: Manickam R. Sridhar, Aniruddha Mukherjee, John L. Moran, III
  • Patent number: 5337332
    Abstract: A received alternate pattern segment is demodulated by a DEM (13), and a power of a demodulated baseband signal is calculated by a power calculator (15). The calculated power is multiplied with a predetermined constant .alpha. by a constant multiplier (16). A power of a signal obtained by removing a frequency component (1/2) the baud rate frequency from the baseband signal output from a BEF (14) is calculated by a power calculator (15'). An adder/subtracter (17) compares the powers by subtracting the two signals, and the sign of the comparison result is discriminated by a sign discriminator (19), thereby detecting an alternate pattern segment and the start point of a pseudo pattern sequence. Furthermore, a count value of a counter (110) is monitored, and when a detection state of an alternate pattern segment continues for a predetermined period of time, it is determined that an alternate pattern segment is detected in practice.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: August 9, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Yaguchi, Koichi Tanaka
  • Patent number: 5331665
    Abstract: A decoder device (VD) used for decoding digital messages according to the Viterbi convolutional decoding algorithm. This Viterbi decoder (VD) may be integrated in a portion of a single electronic chip for inclusion in a receiver of a handportable mobile station of a digital cellular radio system. The decoder (VD) includes a first module (VITALFA) to calculate transition probabilities for the possible state transitions between two successive states of the decoder, and a second module (VIPROB) to calculate, as a function of the state transition probabilities, path probabilities for the possible paths constituted by successive state transitions and ending in each of these states, and to select the path having the highest path probability value.
    Type: Grant
    Filed: May 5, 1992
    Date of Patent: July 19, 1994
    Assignee: Alcatel N.V.
    Inventors: Hans J. J. Busschaert, Peter P. F. Reusens, Ronny M. A. Van Camp
  • Patent number: 5331669
    Abstract: An improved pulse converter for converting a stream of asynchronous input pulses of undetermined duration into a stream of synchronous output pulses of standard duration. The input pulses may occur in any phase or frequency relationship to the reference with the limitation that the input pulses must not occur more frequently than one period of a reference clock plus one synchronizer input hold time and one synchronizer setup time. Additionally, the input pulses must be at least as wide as required to set an input flip-flop. The inventive asynchronous pulse converter requires only two flip-flops, a synchronizer, and a single Exclusive-OR gate, and a single reference clock.
    Type: Grant
    Filed: May 6, 1992
    Date of Patent: July 19, 1994
    Assignee: Ologic Corporation
    Inventors: James H. Wang, Julia W. Wang
  • Patent number: 5331666
    Abstract: An adaptive maximum likelihood demodulator for demodulating digital radio signals on a channel which contains impairments like inter-symbol interference, frequency errors or distortion, that vary with time. The demodulator does not employ channel models to generate signal predictions but rather directly updates the signal predictions for each state without going through the intermediate step of updating a channel model.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: July 19, 1994
    Assignee: Ericsson GE Mobile Communications Inc.
    Inventor: Paul W. Dent
  • Patent number: 5329552
    Abstract: The present invention relates to a method of binary encoding the N points of a constellation corresponding to the discrete positions, in amplitude and in phase, associated with the encoding of binary words in the case of a multicarrier modulation of OFDM type (Orthogonal Frequency Division Multiplexing) of a digitized signal. According to the method, two adjacent points of the constellation correspond to binary words which differ from one another by at most two bits. The present invention applies in particular to digital television.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: July 12, 1994
    Assignee: Thomson-CSF
    Inventors: Tristan de Couasnon, Raoul Monnier, Yvon Fouche, Jean-Bernard Rault
  • Patent number: 5317596
    Abstract: A method of echo cancellation in a full-duplex data communication system with discrete multitone modulation, comprised of an initial step of initializing a set of frequency-domain echo parameters and a set of corresponding time-domain echo parameters, and further including the repeating steps of block multiplying a frequency-domain transmit block of a transmitted signal by the set of frequency-domain echo parameters to produce a frequency-domain echo, converting the frequency-domain transmit block to a time-domain transmit block, subtracting the end of the previous time-domain transmit block from the end of the current time-domain transmit block, performing a convolution of the adjusted time-domain transmit block and the time-domain echo parameters to produce a time-domain echo, subtracting the time-domain echo from a time-domain receive block of a received signal, converting the resulting signal to the frequency-domain to produce a frequency-domain receive block, subtracting the frequency-domain echo from th
    Type: Grant
    Filed: December 1, 1992
    Date of Patent: May 31, 1994
    Assignee: The Board of Trustees of the Leland Stanford, Junior University
    Inventors: Minnie Ho, John M. Cioffi
  • Patent number: 5317603
    Abstract: Isochronous interface apparatus for transferring data from a source over a clocked channel to a destination. A channel input interface is interposed between the source and the channel. The channel input interface includes a data compressor adapted to compress the data with a compression ratio responsive to a signal. A first elastic buffer is coupled between the data compressor and the channel, having a first variable stack and providing a first signal representing the depth of the first variable stack. The first elastic buffer has an input coupled to the data compressor and has an output clocked by the channel and provides a signal representing the depth of the variable stack. The first signal is feedback to the data compressor for controlling the compression ratio of the data compressor. A channel output interface is interposed between the clocked channel and the destination. The channel output interface includes a data expander coupled to the channel.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: May 31, 1994
    Assignee: GTE Government Systems Corporation
    Inventor: Josef Osterweil
  • Patent number: 5317600
    Abstract: The channel frequency of a digital radiotelephone is coarse tuned utilizing the phase information of the symbols. According to the invention the phase change between the measured phases of one or more received symbols (d) and the previous symbol (e) is detected, the phase change being compared with allowed phase changes. Based on this a decision (g) is made concerning the phase of the transmitted symbol, the phase error (f.sub.err) or difference between the decision (g) and the measured phase change (d) is generated, and on this basis the channel frequency is adjusted.
    Type: Grant
    Filed: May 12, 1992
    Date of Patent: May 31, 1994
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Antti Kansakoski
  • Patent number: 5317604
    Abstract: Method of transferring isochronous data from a source over a clocked channel to a sink. The data is compressed by a compression ratio responsive to a depth of a first variable stack. The compressed data is stored in the first stack and clocked by the channel. Compressed data on the channel is expanded and stored in a second variable stack. The variable stack is clocked to maintain the second variable stack at a constant depth.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: May 31, 1994
    Assignee: GTE Government Systems Corporation
    Inventor: Josef Osterweil
  • Patent number: 5317595
    Abstract: A method for use in a digital data transfer apparatus, such as a radio telephone (10), that includes an adaptive equalizer, such as an adaptive filter (32), for receiving, correcting, and outputting data symbols. The method determines correction coefficients for the adaptive equalizer and includes a first step of, for every data symbol output by the adaptive equalizer, maintaining a first matrix R that is a NxN channel correlation matrix and a second matrix P that is a N.times.1 cross correlation vector between a received signal and a transmitted symbol. The method includes a second step of, for every k.sup.th symbol output by the adaptive equalizer, determining a set of correction coefficients (C) for the adaptive equalizer based upon the matrices R and P. A third step of the method applies the set of determined correction coefficients to the adaptive equalizer so as to optimally correct a subsequently received data symbol.
    Type: Grant
    Filed: June 30, 1992
    Date of Patent: May 31, 1994
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Kjell Ostman
  • Patent number: 5317601
    Abstract: Techniques for providing a number of precisely synchronized clock signals at a number of different frequencies at each of a plurality of locations on a chip. A number of synchronized clock signals are generated at an initial location on the chip, and distributed to the various locations with relative delay times that are equal to within a precision, which may be less than the ultimate precision required. A single synchronization signal is also generated at the initial location, and is distributed to the remote locations with delay times that are equal to each other to a precision that corresponds to the precision required of all the clock signals. Separate synchronization circuitry at each remote location receives the clock signals and the synchronization signal, and resynchronizes the clock signals to the precision with which the synchronization signal was distributed. The set of lines is configured as a tree structure.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: May 31, 1994
    Assignee: Silicon Graphics
    Inventors: Thomas J. Riordan, Albert M. Thaik, Hai N. Nguyen
  • Patent number: 5313499
    Abstract: A Phase Lock Loop (PLL) receives input signals from a local area network (LAN) and recovers data and clock signals therefrom. The PLL includes a charge pump which is responsive to pump-up or pump-down signals provided by a phase detector. A level determination circuitry scales the charge pump current in proportion to the time elapsing between transitions in the input signals. The charge pump, phase detector and level determination circuitry provide a constant average amps per radian gain and is insensitive to variations in the input signals.
    Type: Grant
    Filed: April 29, 1992
    Date of Patent: May 17, 1994
    Assignee: International Business Machines Corporation
    Inventor: Ronald L. Coburn
  • Patent number: 5305355
    Abstract: A data communication system for use on a motor vehicle includes at least one master unit and at least one slave unit which are connected to a communication bus. When the master unit is enabled, the master controller of the master unit outputs connection request demand data to the slave unit. The slave unit has a slave controller which transmits its own connection request information to the master unit in response to the connection request demand data from the master unit. The slave controller transmits, to the master unit, first change information indicating whether the connection information stored in a first memory and connection information of the slave unit that has been transmitted to the master unit are identical to each other or not. The master controller transmits some or all of connection information stored in a second memory to slave units based on the first change information of the slave units.
    Type: Grant
    Filed: April 27, 1992
    Date of Patent: April 19, 1994
    Assignee: Pioneer Electronic Corporation
    Inventors: Yasunao Go, Yoshikatsu Ikata, Toshiyuki Kimura, Hiroshi Shimotsuma
  • Patent number: 5304990
    Abstract: A modular traffic analyzer for one or more digital signal multipath transmission channels for the management of digital or analog telephone installations including a module for acquiring and storing samples and a module for processing the latter. A module including at least one dedicated discrimination circuit per signal type travelling over the channel is provided so as to perform, from spectral and power values of the digital signal, a compression of discriminated parameter signal and a distribution according to the signal type or in a temporal mode with respect to one or more channels.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: April 19, 1994
    Assignee: France Telecom
    Inventors: Jean-Claude Rebourg, Serge JeanClaude, Philippe Ezran
  • Patent number: 5305353
    Abstract: The invention provides a method and apparatus for transmitting digital signal information to a receiver using a plurality of antennas. The invention involves applying a channel code to a digital signal producing one or more symbols. A plurality of symbol copies is made and each copy is weighted by a distinct time varying function. Each antenna transmits a signal based on one of the weighted symbol copies. Any channel code may be used with the invention, such as a convolutional channel code or block channel code. Weighting provided to symbol copies may involve application of an amplitude gain, phase shift, or both. The present invention may be used in combination with either or both conventional interleavers and constellation mappers.
    Type: Grant
    Filed: May 29, 1992
    Date of Patent: April 19, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Vijitha Weerackody
  • Patent number: 5303267
    Abstract: Standard multipoint junction units (MJUs) are used in parallel-connected MJU sets for a private multipoint data communications network. The MJU sets provide communications between remote terminals and a central site at rates faster than those provided by a stand-alone MJU. On the remote terminal side of the MJU set, data from a remote terminal on two or more adjacent channels are carried on a multichannel transmission line, such as a T1 line, to a transmission line port unit. Adjacent output channels from the port unit are connected to branch ports of each MJU of the MJU set, such that the branch port of each MJU that is associated with that terminal receives one channel. On the central site side of the MJU set, adjacent channels are connected from a transmission line port unit to the master input of each MJU. Connections between the MJU ports and the port units are through a time slot interchange matrix, which ensures that the data is maintained in its proper sequence.
    Type: Grant
    Filed: May 4, 1992
    Date of Patent: April 12, 1994
    Assignee: DSC Communications Corporation
    Inventor: Sudhir Gupta