Patents Examined by Eric Cardwell
  • Patent number: 11630607
    Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 18, 2023
    Assignee: Rambus Inc.
    Inventor: Frederick Ware
  • Patent number: 11625328
    Abstract: The described technology is generally directed towards detecting and propagating changes that affect information maintained in a cache. Data may be pre-cached in advance of its actual need, however such data can change, including in various different source locations. A change monitoring/signaling service detects relevant changes and publishes change events to downstream listeners, including to a cache population service that updates pre-cache data as needed in view of such data changes. Per-user-specific data also may be pre-cached, such as when a user logs into a data service.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: April 11, 2023
    Assignee: HOME BOX OFFICE, INC.
    Inventor: Michal M. Bryc
  • Patent number: 11620072
    Abstract: A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: recording a valid count of each physical erasing unit in a plurality of physical erasing units; sequentially arranging M physical erasing units corresponding to each of chip enable groups according to the valid count to form a plurality of sorted physical erasing units; remapping the physical erasing units corresponding to M virtual blocks according to the plurality of sorted physical erasing units; calculating a total number of valid counts of the remapped M virtual blocks, and sequentially arranging the remapped M virtual blocks according to the total number of valid counts to form a plurality of sorted virtual blocks; and sequentially extracting at least one of the sorted virtual blocks as a source virtual block to perform a garbage collection operation.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: April 4, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventor: Chong Peng
  • Patent number: 11620059
    Abstract: A first set of applications that require a higher performance in comparison to a second set of applications are identified, and a first set of filesets corresponding to the first set of applications are identified. In response to a copy on write based snapshot operation with respect to the first set of filesets, blocks that are overwritten are stored in a first storage device that is of a higher performance in comparison to a second storage device.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: April 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sandeep Ramesh Patil, Wei Gong, Smita J. Raut, Sasikanth Eda, Gautam H. Shah
  • Patent number: 11615032
    Abstract: A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: March 28, 2023
    Assignee: Arm Limited
    Inventors: Matthew James Horsnell, Grigorios Magklis, Richard Roy Grisenthwaite
  • Patent number: 11609718
    Abstract: Staging data on a storage element integrating fast durable storage and bulk durable storage, including: receiving, at a storage element integrating fast durable storage and bulk durable storage, a data storage operation from a host computer; storing data corresponding to the data storage operation within fast durable storage in accordance with a first data resiliency technique; and responsive to detecting a condition for transferring data between fast durable storage and bulk durable storage, transferring the data from fast durable storage to bulk durable storage in accordance with a second data resiliency technique.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: March 21, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Ronald Karr, Constantine Sapuntzakis, Mark McAuliffe, Farhan Abrol, Neil Vachharajani, Timothy Brennan
  • Patent number: 11593034
    Abstract: A simulated stretched volume may be configured from multiple volumes of a single data storage system. The volumes may be assigned unique identifiers. The volumes may be exposed to a host over paths from the single data storage system as the same volume having the same unique identifier. The single data storage system may include sets of target ports with each set simulating paths to a different data storage system. A management command may be received that is directed to the simulated stretched volume having the unique identifier. The management command may be received on a path from the host to a target port of the single data storage system. Servicing the management command may include the single data storage system simulating either the local or remote system depending on the set of target ports including the target port.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: February 28, 2023
    Assignee: Dell Products L.P.
    Inventors: Yuri Stotski, Kirill Zabelin, Chen Reichbach, Yuval Harduf
  • Patent number: 11593027
    Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert M. Walker
  • Patent number: 11593036
    Abstract: Staging data on a storage element integrating fast durable storage and bulk durable storage, including: receiving, at a storage element integrating fast durable storage and bulk durable storage, a data storage operation from a host computer; storing data corresponding to the data storage operation within fast durable storage in accordance with a first data resiliency technique; and responsive to detecting a condition for transferring data between fast durable storage and bulk durable storage, transferring the data from fast durable storage to bulk durable storage in accordance with a second data resiliency technique.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 28, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Ronald Karr, Constantine Sapuntzakis, John Colgrove
  • Patent number: 11579778
    Abstract: A method for synchronous replication of stream data includes receiving a stream of data blocks for storage at a first storage location associated with a first geographical region and at a second storage location associated with a second geographical region. The method also includes synchronously writing the stream of data blocks to the first storage location and to the second storage location. While synchronously writing the stream of data blocks, the method includes determining an unrecoverable failure at the second storage location. The method also includes determining a failure point in the writing of the stream of data blocks that demarcates data blocks that were successfully written and not successfully written to the second storage location. The method also includes synchronously writing, starting at the failure point, the stream of data blocks to the first storage location and to a third storage location associated with a third geographical region.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 14, 2023
    Assignee: Google LLC
    Inventors: Pavan Edara, Jonathan Forbes
  • Patent number: 11567704
    Abstract: A method for storing data, comprising receiving, by a file system (FS) client executing on an offload component, a first request from a translation module, wherein the translation module translated a second request that was to be performed on an emulated block device into the first request, wherein the first request is specified using file semantics, wherein the first request is associated with data, wherein the offload component is located in a hardware layer of a client application node, and wherein the translation module is located on the offload component, and processing the first request by the FS client and a memory hypervisor module, wherein the FS client and the memory hypervisor module are executing in a modified client FS container on the offload component, wherein processing the first request results in at least a portion of the data being stored in a location in a storage pool.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: January 31, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jean-Pierre Bono, Marc A. De Souter
  • Patent number: 11561701
    Abstract: Embodiments are directed to a method and system of forecasting a disk drive survival period in a data storage network, by obtaining operating system data and manufacturer data for the disk drive to create a dataset, screening the dataset to identify a number of features to be selected for model creation, wherein the data set includes censored data and non-censored data, and performing, in an analytics engine, semi-parametric survival analysis on the data set using transfer learning on the model to provide a time-based failure prediction of the disk drive. A graphical user interface provides to a user the failure prediction in one of text form or graphical form.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: January 24, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Jitendra Singh, Rahul Deo Vishwakarma
  • Patent number: 11550509
    Abstract: Accordingly the embodiments herein provide a method for adaptive data transfer in a memory system (140), the method comprising: receiving at least one of a data copy request and a data transfer request to perform at least one of a data copy and a data transfer form a first memory subsystem (142) to a second memory subsystem (144). Configuring the memory system (140) in one of a first memory mode and a second memory mode based on a time required to perform at least on of data transfer and data transfer from the first memory subsystem (142) to the second memory subsystem (144) using an enhanced system model and performing at least one of data transferring and data copying from the first memory subsystem (142) to the second memory subsystem (144) in one of the first configured memory mode and the second configured memory mode.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: January 10, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Abhishek Kumar Singh, Ekansh Gupta, Manjunath Jayram, Yunas Rashid, Mahantesh Mallikarjun Kothiwale
  • Patent number: 11537310
    Abstract: Replication of data from a primary computing system to a secondary computing system. The replication is single-threaded or multi-threaded depending on one or more characteristics of the data to be replicated. As an example, the characteristics could include the type of data being replicated and/or the variability on that data. Also, the multi-threading capabilities of the primary and secondary computing systems are determined. Then, based on the identified one or more characteristics of the data, the primary computing system decides whether to perform multi-threaded replication and the multi-threading parameters of the replication based on the one or more characteristics of that data, as well as on the multi-threading capabilities of the primary and secondary computing system.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 27, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Deepak Verma, Kesavan Shanmugam, Michael Gregory Montwill
  • Patent number: 11537297
    Abstract: The present disclosure is related to methods, systems, and machine-readable media for deleting snapshot pages using sequence numbers and page lookups. A monotonically-increasing sequence number (SN) can be assigned to each created page of a first snapshot of a storage volume. A first snapshot sequence number (snapSN) can be assigned to the first snapshot responsive to a creation of a second snapshot, wherein the first snapSN is equal to a largest SN of the first snapshot. An SN can be assigned to each created page of the second snapshot, wherein a first page of the second snapshot is assigned an SN monotonically increased from the first snapSN. A second snapSN can be assigned to the second snapshot responsive to a creation of a third snapshot, wherein the second snapSN is equal to a largest SN of the second snapshot. An SN can be assigned to each created page of the third snapshot, wherein a first page of the third snapshot is assigned an SN monotonically increased from the second snapSN.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: December 27, 2022
    Assignee: VMware, Inc.
    Inventors: Enning Xiang, Wenguang Wang, Pranay Singh, Subhradyuti Sarkar
  • Patent number: 11531477
    Abstract: An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 20, 2022
    Assignee: LEXMARK INTERNATIONAL, INC.
    Inventors: Stephen Porter Bush, Jennifer Topmiller Williams
  • Patent number: 11526292
    Abstract: Data may be replicated from a host storage system to a target storage system. It may be determined to replicate a first logical storage element on the source storage system to a second logical storage element on the target storage system, wherein the first logical storage element defines a first data portion having a first value. It may be determined that a third logical storage element on the target storage system defines a second data portion having the first value. The first logical storage element may be replicated to the second logical storage element by establishing a deduplication relationship between the second logical storage element and the third logical storage element on the target storage system without transmitting the first data portion from the source storage system to the target storage system.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 13, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Benjamin Yoder, William R. Stronge
  • Patent number: 11507325
    Abstract: A storage apparatus includes a processor and a memory. The processor provides a plurality of logical volumes each allowing input and output of data, and processes each data input to and output from a storage device via the logical volume. The processor acquires operational data associated with each of the plurality of logical volumes, and transmits the acquired operational data to a source of a operational data request. The processor adjusts, for each of the logical volumes, accuracy of the operational data to be acquired from each of the logical volumes, according to a status of each of the logical volumes.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: November 22, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Kenta Sato, Kazuei Hironaka, Akira Deguchi
  • Patent number: 11500765
    Abstract: An application program stored in a ROM includes a function lookup data structure in which functions called by the application program have identifiers and memory addresses at which the function is located and can be executed. Upon startup, the function lookup data structure is copied to a RAM as a revised lookup data structure and is compared to a revision lookup data structure also written to that RAM or elsewhere. If the revision lookup data structure contains replacement functions having the same function identifiers but new memory addresses, these new memory addresses are written over the existing addresses in the revised lookup data structure for those replacement functions. The application program refers to the revised lookup data structure to find and execute the functions; thus the original application program on the ROM can continue to be used with revised functions.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: November 15, 2022
    Assignee: ABBOTT DIABETES CARE INC.
    Inventors: Xuandong Hua, Kurt Leno
  • Patent number: 11487460
    Abstract: In some embodiments, a storage system comprises at least one processor coupled to memory. The processor is configured to obtain a write operation that comprises first data associated with a logical data device and to store the first data in a first entry of a log-structured array (LSA). The at least one processor is configured to invalidate a second entry based at least in part on the storage of the first data in the first entry. The second entry comprises second data associated with the logical data device that was stored in the second entry prior to obtaining the write operation. The at least one processor is configured to determine that a first indication in LSA metadata associated with the LSA indicates that the invalidated second entry comprises data that is awaiting replication and to defer reclamation of the second entry based at least in part on the determination.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: November 1, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Itay Keller, Dan Aharoni