Patents Examined by Eric Cardwell
  • Patent number: 11275529
    Abstract: Maintenance management on backup storage systems. Specifically, the disclosed method and system derive backup storage system load from a collection of profiled load factoring features. The backup storage system load may subsequently drive whether maintenance operations may be deferred to projected non-peak load times or, alternatively, may be permitted to proceed.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 15, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Gururaj Kulkarni, Priyank Tiwari, Michal Jacek Drozd
  • Patent number: 11269770
    Abstract: Techniques involve managing a storage space. In response to receiving an allocation request for allocating a storage space, a storage space size and a slice size are obtained. A first storage system and a second storage system are selected from multiple storage systems, the first storage system and the second storage system includes a first storage device group and a second storage device group respectively, and the first storage device group does not overlap the second storage device group. A first slice group and a second slice group is obtained from the first storage system and the second storage system respectively, on the basis of the size of the storage space and the size of the slice. A user storage system is built at least on the basis of the first slice group and the second slice group, so as to respond to the allocation request.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 8, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Xinlei Xu, Xiongcheng Li, Lifeng Yang, Geng Han, Jian Gao
  • Patent number: 11256533
    Abstract: A processing device in a host computer system receives an instruction to write data to a storage device coupled to the host computer system and store a copy of the data in a cache of the host computer system. The processing device initiates a write operation to write the data from the cache to the storage device and detects that the storage device is disconnected from the host computer system during execution of the write operation. In response to detecting that the storage device is disconnected, the processing device may suspend execution of at least one of a virtual machine or a process that issued the first instruction. After determining that the storage device is reconnected to the host computer system, the processing device can resumes the write operation to continue writing the data from the cache to the storage device.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: February 22, 2022
    Assignee: Parallels International GmbH
    Inventors: Alexander Grechishkin, Konstantin Ozerkov, Alexey Koryakin, Nikolay Dobrovolskiy, Serguei Beloussov
  • Patent number: 11243701
    Abstract: The present invention provides a data write method and a solid-state drive array. The solid-state drive array is based on a RAID system and includes n solid-state drives. Before to-be-written data is written into the solid-state drive array, the to-be-written data is divided into n data blocks that are in a one-to-one correspondence with the n solid-state drives. After the n data blocks are all stored into the corresponding solid-state drives, FTL update of the n data blocks is performed, to complete write of the to-be-written data. If the solid-state drive array is powered off during storage of the n data blocks, because FTL update of the data blocks is not performed, all the n data blocks fail to be written into the solid-state drive array, thereby ensuring atomicity of write operations of the n data blocks.
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: February 8, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Dengben Wu, Xiaoxin Xu, Junjie Wang
  • Patent number: 11231861
    Abstract: An apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to control delivery of input-output (IO) operations from a host device to at least first and second storage systems over selected ones of a plurality of paths through a network, the first and second storage systems being arranged in an active-active configuration relative to one another. The processing device is further configured to identify one or more logical storage devices that are each accessible via at least first and second different ones of the paths to respective ones of the first and second storage systems, and to modify path selection for IO operations directed to the one or more identified logical storage devices relative to path selection for IO operations directed to one or more other logical storage devices. The processing device illustratively comprises at least a portion of the host device.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: January 25, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Vinay G. Rao, Arieh Don
  • Patent number: 11204713
    Abstract: Techniques for processing data may include: receiving a write operation that writes first data to a first storage device of a first data storage system that is configured for replication on a second storage device of a second data storage system; and replicating the first data on the second storage device on the second data storage system. The replicating may include identifying the first data of the first storage device to be replicated on the second storage device of the second data storage system; selecting a compression technique in accordance with an expected wait delay of the first data, wherein the first expected wait delay denotes an amount of time the first bucket of data is expected to wait before transmission to the second data storage system; compressing the first data using the selected first compression technique; and sending the compressed first data to the second data storage system.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 21, 2021
    Assignee: EMC IP Holding Company LLC
    Inventor: Venkata L R Ippatapu
  • Patent number: 11204704
    Abstract: Technologies are described herein for remotely configuring multi-mode dual in-line memory modules (“multi-mode DIMMs”) using a firmware or a baseboard management controller (“BMC”). Technologies are also described for simultaneously initiating multiple commands for configuring multi-mode DIMMs using a BMC and for updating inventory data regarding multi-mode DIMMs stored by a BMC.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: December 21, 2021
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Manish Jha, Harikrishna Doppalapudi, Manickavasakam Karpagavinayagam, Igor Kulchytskyy, Gopinath Sekaran, Altaf Hussain, Manikandan Palaniappan, Shirley Heby Hubert
  • Patent number: 11194494
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding stream. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding streams. As the parity data is updated, the corresponding command is simultaneously written to the corresponding stream.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: December 7, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Daniel L. Helmick, Peter Grayson
  • Patent number: 11194509
    Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 7, 2021
    Assignee: Rambus Inc.
    Inventor: Frederick Ware
  • Patent number: 11194723
    Abstract: The prefetch control is optimized according to a data pattern. The model selection unit selects inference units from outside of the device driver and replace each of the inference units according to the type of data analysis. The inference units, each of which is a neural network, predict an address region of the SSD based on I/O trace data collected by the device driver and instruct the device driver to prefetch from the outside based on the prediction result. The prefetch execution unit performs prefetch for the storage cache allocated to the SCM based on the prediction by a neural network associated with the query and the database.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 7, 2021
    Assignee: HITACHI, LTD.
    Inventor: Yuji Saeki
  • Patent number: 11194479
    Abstract: A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventor: Chan-Jong Woo
  • Patent number: 11188469
    Abstract: A block-based storage system may implement page cache write logging. Write requests for a data volume maintained at a storage node may be received at a storage node. A page cache for may be updated in accordance with the request. A log record describing the page cache update may be stored in a page cache write log maintained in a persistent storage device. Once the write request is performed in the page cache and recorded in a log record in the page cache write log, the write request may be acknowledged. Upon recovery from a system failure where data in the page cache is lost, log records in the page cache write log may be replayed to restore to the page cache a state of the page cache prior to the system failure.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 30, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Danny Wei, John Luther Guthrie, II, James Michael Thompson, Benjamin Arthur Hawks, Norbert P. Kusters
  • Patent number: 11182257
    Abstract: The disclosure provides methods and systems to perform data backups of protected data. According to an embodiment, a nominal backup schedule is received, and a time differential between the nominal backup schedule and a current time metric is determined. If the time differential is greater than a threshold, the backup schedule is modified so that times indicated in the modified backup schedule are at a higher frequency than a frequency of the indicated times of the nominal backup schedule. In another embodiment, if a reliability metric is greater than a corresponding threshold, the backup schedule is modified so that times indicated in the modified backup schedule are at a higher frequency than a frequency of the indicated times of the nominal backup schedule.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: November 23, 2021
    Assignee: Datto, Inc.
    Inventors: Robert J. Gibbons, Jr., William Robert Speirs, II, Neale Campbell Hutcheson, Jr., Robert Loce
  • Patent number: 11157402
    Abstract: A memory system includes a memory device including plural blocks, each capable of storing data, and a controller coupled with the memory device. The controller can generate a blocklist including a valid page count for at least one target block among the plural blocks before updating a map data, update the map data and the valid page count of the at least one target block, compare the previous valid page count stored in the blocklist with the updated valid page count, and erase invalid map data of the at least one target block according to a comparison result.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11151054
    Abstract: A central processing unit (CPU) sets a cache lookup operation to a first mode in which the CPU searches a cache and only performs an address translation in response to a cache miss. The CPU performs the cache lookup operation while in the first mode using an address that results in a cache miss. Responsive to the CPU detecting the cache miss, the CPU sets the cache lookup operation from the first mode to a second mode in which the CPU concurrently searches the cache and performs an address translation. The CPU performs a cache lookup operation while in the second mode using a second address that results in a cache hit. Responsive to detecting the cache hit, the CPU sets the cache lookup operation from the second mode to the first mode. This process repeats in cycles upon detection of cache hits and misses.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Naga P. Gorti, Mohit Karve
  • Patent number: 11144232
    Abstract: An apparatus includes at least one processing device, with the at least one processing device being configured, in conjunction with synchronous replication of at least one logical storage volume between first and second storage systems arranged in an active-active configuration, to create a first snapshot of the logical storage volume in the first storage system, to create a second snapshot of the logical storage volume in the second storage system, to create a third snapshot of the logical storage volume in the first storage system, to initiate an asynchronous replication cycle to transfer differential data between the first and the third snapshots in the first storage system to the second storage system, and to utilize the second snapshot and the transferred differential data to create an additional snapshot of the logical storage volume in the second storage system that is synchronized with the third snapshot in the first storage system.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: October 12, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Xiangping Chen, David Meiri
  • Patent number: 11138082
    Abstract: A plurality of storage nodes is provided. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. The plurality of storage nodes is configured to initiate an action based on the redundant copies of the metadata, responsive to achieving a level of redundancy for the redundant copies of the metadata. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: October 5, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, John Davis, Brian Gold, Shantanu Gupta, Robert Lee, Igor Ostrovsky, Rusty Sears
  • Patent number: 11132138
    Abstract: A computer-implemented method, according to one approach, is for converting an existing storage pool into an intended storage pool in place. The computer-implemented method includes: identifying a request to convert the existing storage pool having a first extent size into the intended storage pool having a second extent size, where the first extent size is larger than the second extent size. For each volume in the existing storage pool: a temporary pause/lock is performed on a volume segment table (VST) entry which corresponds to the given volume, and a new structure is applied to the VST entry. The new structure divides existing physical extents associated with the VST entry into two or more smaller physical extents. Furthermore, for each of the ranks in the existing storage pool, the given rank is converted from the first extent size to the second extent size.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Clint A. Hardy, Karl Allen Nielsen, Matthew Joseph Kalos
  • Patent number: 11106371
    Abstract: Example implementations described herein are directed to Input/Output (I/O) path reservation with out of band management. In example implementations, for failure of a storage orchestrator to delete the path between the container and the first volume, the example implementations described herein are directed to deleting a path between the first volume and a quorum volume; and establishing an I/O path between the new container and the second volume.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 31, 2021
    Assignee: Hitachi, Ltd.
    Inventors: Akiyoshi Tsuchiya, Tomohiro Kawaguchi
  • Patent number: 11106590
    Abstract: The described technology is generally directed towards detecting and propagating changes that affect information maintained in a cache. Data may be pre-cached in advance of its actual need, however such data can change, including in various different source locations. A change monitoring/signaling service detects relevant changes and publishes change events to downstream listeners, including to a cache population service that updates pre-cache data as needed in view of such data changes. Per-user-specific data also may be pre-cached, such as when a user logs into a data service.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: August 31, 2021
    Assignee: HOME BOX OFFICE, INC.
    Inventor: Michal M. Bryc