Abstract: An image sensor includes a first light detecting device configured to selectively sense or absorb first visible light, a second light detecting device configured to selectively sense or absorb second visible light having a longer wavelength region than the first visible light, and a third light detecting device on the first light detecting device and the second light detecting device. The first light detecting device has one of a maximum transmission wavelength and a maximum absorption wavelength less than about 440 nm, the second light detecting device has one of a maximum transmission wavelength and a maximum absorption wavelength greater than about 630 nm, and the third light detecting device is configured to selectively sense or absorb third visible light having a wavelength region between the first visible light and the second visible light.

Abstract: Manufacturing an MRAM device may include forming an upper electrode on a magnetic tunnel junction stack, where the stack may include a lower electrode layer, a magnetic tunnel junction layer and a middle electrode layer that are sequentially formed on an insulating interlayer and a lower electrode contact on a substrate. The upper electrode may be formed on the middle electrode layer. An upper electrode protective structure may be formed to cover at least a sidewall and an upper surface of the upper electrode. The middle electrode layer, the magnetic tunnel junction layer and the lower electrode may be patterned by an etching process to form a middle electrode, a magnetic tunnel junction pattern and a lower electrode, respectively. The upper electrode protective structure may isolate the upper electrode from exposure during the patterning, and the upper electrode protective structure may remain on the upper electrode subsequently to the patterning.

Abstract: A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.

Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

Abstract: Provided are an electron beam curable resin composition including polymethylpentene, and a crosslinking agent, in which the crosslinking agent has a saturated or unsaturated ring structure, at least one atom among atoms forming at least one ring is bonded to any allylic substituent of an allyl group, a methallyl group, an allyl group through a linking group, and a methallyl group through a linking group, and a molecular weight is 1,000 or less, a resin frame for reflectors using the resin composition, a reflector, and a molding method using the resin composition.

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes a first source terminal formed of a material and connected to a first source, a first drain terminal formed of the material and connected to a first drain, a first gate overlapping a portion of the substrate that is between the first source and the first drain, and a first dielectric layer between the first gate and the substrate. The second transistor includes a control gate formed of the material and overlapping a part of the substrate that is positioned between a second source and a second drain, a second dielectric layer between the control gate and the substrate, a floating gate extending through the second dielectric layer to contact a doped region in the substrate, and an insulating member positioned between the control gate and the floating gate.

Abstract: Disclosed herein is a composite magnetic sealing material includes a resin material and a filler blended in the resin material in a blend ratio of 50 vol. % or more and 85 vol. % or less. The filler includes a first magnetic filler containing Fe and 32 wt. % or more and 39 wt. % or less of a metal material composed mainly of Ni, the first magnetic filler having a first grain size distribution, and a second magnetic filler having a second grain size distribution different from the first grain size distribution.

Abstract: The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.

Abstract: A display device is disclosed. In one aspect, the display device includes a substrate, a barrier layer formed over the substrate, and an emission layer formed over the barrier layer. The display device also includes a stress-absorbing layer contacting one of the substrate, the barrier layer, and the emission layer. The stress-absorbing layer has a structural density configured to partially vary based on an applied voltage.

Abstract: A thermally conductive sheet, which contains: a binder; carbon fibers; and an inorganic filler, wherein the thermally conductive sheet is to be sandwiched between a heat source and a heat dissipation member of a semiconductor device, wherein the carbon fibers have an average fiber length of 50 ?m to 250 ?m, wherein thermal resistance of the thermally conductive sheet is less than 0.17 K·cm2/W, as measured in accordance with ASTM-D5470 with a load of 7.5 kgf/cm2, and wherein the thermally conductive sheet has an average thickness of 500 ?m or less.

Abstract: A semiconductor device having a stacked structure formed by stacking a thinned first silicon substrate and a second silicon substrate supporting the first silicon substrate, wherein the first silicon substrate includes a first surface with a crystal surface orientation of (100) or (110) and a second surface opposite to the first surface, the second silicon substrate includes a third surface and a fourth surface that is opposite to the third surface and from which a silicon surface with a crystal surface orientation (111) is exposed, and wherein the semiconductor device is formed by etching silicon with a predetermined thickness in a direction from the first surface toward the second surface to make the first silicon substrate to be thinned, after bonding the first silicon substrate and the second silicon substrate in a state where the second surface and the third surface facing the second surface are bonded with each other.

Abstract: A semiconductor device for flame detection, including: a semiconductor body having a first conductivity type conductivity, delimited by a front surface and forming a cathode region; an anode region having a second conductivity type conductivity, which extends within the semiconductor body, starting from the front surface, and forms, together with the cathode region, the junction of a photodiode that detect ultraviolet radiation emitted by the flames; a supporting dielectric region; and a sensitive region, which is arranged on the supporting dielectric region and varies its own resistance as a function of the infrared radiation emitted by the flames.

Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

Abstract: A structure includes a field isolation region in a high resistivity substrate, a compensation implant region under the field isolation region in the high resistivity substrate, where the compensation implant region is configured to substantially eliminate a parasitic p-n junction under the field isolation region. The parasitic p-n junction is formed between trapped charges in the field isolation region and the high resistivity substrate. The compensation implant region includes a charge of a first conductivity type to compensate a parasitic charge of a second conductivity type under the field isolation region. The compensation implant region is configured to improve linearity of RF signals propagating through a metallization layer over the field isolation region. The structure further includes a deep trench extending through the field isolation region and the compensation implant region, and a damaged region adjacent the deep trench.

Abstract: A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.

Abstract: Disclosed herein is a light-emitting diode (LED) package in accordance with an embodiment of the present invention, which includes an LED configured to provide light of a wavelength having a specific region, a circuit board electrically connected to the LED through bonding pads formed at the bottom of the LED, a phosphor layer formed as a cap, disposed to surround sides and a top of the LED, and configured to have sides and top thereof formed to a uniform thickness, and a buffer layer disposed between the top of the LED and a bottom of the phosphor layer and configured to suppress heat, generated from the top of the LED, from being transferred to the bottom of the phosphor layer and to prevent a bottom of the phosphor layer from being deviated from the top of the LED.

Abstract: A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for example, 8500 volts) without suffering breakdown. A P type peripheral aluminum diffusion region extends around the bottom periphery of a thick die. The peripheral aluminum diffusion region extends upward from the bottom surface of the die, extending into N- type bulk silicon. A deep peripheral trench extends around the upper periphery of the die. The deep trench extends from the topside of the die down toward the peripheral aluminum diffusion region. A P type sidewall doped region extends laterally inward from the inner sidewall of the trench, and extends laterally outward from the outer sidewall of the trench. The P type sidewall doped region joins with the P type peripheral aluminum diffusion region, thereby forming a separation edge diffusion structure that surrounds the active area of the die.

Abstract: A pixel including a photodiode having a first pole coupled through a transfer MOS transistor to a node for sensing charges of a first type stored in the photodiode, and having a second pole connected to a storage capacitor and to a circuit for reading charges of a second type sent to the storage capacitor.

Abstract: A method for fabricating a photosensitive device, comprising: a first step of preparing, on a substrate, at least a first photosensitive portion, active within a range of wavelengths, the first portion being surrounded by a second portion that is inactive. A material, covering the first portion, is selectively arranged into a hydrophilic layer by an electrochemical process. The second portion comprises a hydrophobic material on an upper surface opposite the substrate. The method further comprises the following steps: spraying on the upper surfaces of the first and second portions a liquid comprising a transparent material, and forming a converging lens containing the material, above the first portion.

Abstract: Jitter that becomes a problem in a semiconductor part which performs high-speed signal processing is reduced. A semiconductor device includes a heat-resistant metal plate, a capacitor part having a lower electrode, a sintered dielectric part, and an upper electrode that are formed on one or more surfaces of the heat-resistant metal plate, a semiconductor chip fixed on the capacitor part, a wire for electrically connecting a lead frame to the semiconductor chip and the upper electrode, and a mold part in which at least the capacitor part and the semiconductor chip are buried. The semiconductor chip, the electrode, the metal plate, and the like are electrically connected with each other via first, second, and third wires.