Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a source well having the first conductivity type disposed in the high-voltage well, a drift region disposed in the high-voltage well and spaced apart from the source well, and a gradient implant region having the second conductivity type and disposed in the high-voltage well between the source well and the drift region.

Abstract: A storage device with long data retention time is configured to include a first transistor, a second transistor, and a third transistor. The first transistor controls electrical connection between a first wiring and a gate of the second transistor. The second transistor controls electrical connection between a second wiring and a gate of the third transistor. The off-state current of the first transistor is lower than that of the third transistor. The leakage current of the second transistor is lower than that of the third transistor.

Abstract: A driver IC (Integrated Circuit) includes a power supply terminal; an output terminal to be coupled to a load element; a connection node on a current path between the power supply terminal and the output terminal; a substrate resistance, having one end coupled to the connection node; an output transistor including a gate, wherein the output transistor is coupled in series with the substrate resistance through the connection node; a resistance, having one end coupled to an other end of the substrate resistance; and a voltage detecting circuit configured to detect a voltage depending on a voltage between the one end of the substrate resistance and the other end of the substrate resistance, and to output an output signal, which is as an output of the voltage detecting circuit, to the gate of the output transistor.

Abstract: A TFT array substrate and a manufacturing method of the same are disclosed by the present disclosure. The TFT array substrate includes a base, a light shielding layer, and a low hydrogen layer. The light shielding layer includes a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer includes a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen Poly-Si layer formed on the silicon oxide layer. The layer number of the light shielding layer is equal to that of the low hydrogen layer. The time of manufacturing the light shielding layer matched that of manufacturing the low hydrogen layer, which enhances whole capacity of the TFT array substrate dramatically, and reduces risk of the manufacturing process.

Abstract: A display substrate and a method of manufacturing a display substrate are disclosed. The display substrate includes an active pattern, a first gate electrode and a second gate electrode. The active pattern is disposed on a base substrate. The first gate electrode overlaps the active pattern. The first gate electrode is spaced apart from the active pattern by a first distance. The second gate electrode overlaps the active pattern. The second gate electrode is spaced apart from the active pattern by a second distance which is larger than the first distance.

Abstract: The purpose of the present invention is to reduce the size and thickness of an LED module in which a plurality of LED dies along with other electronic components are mounted on a circuit board, and at the same time to stabilize the operation of the module with respect to source voltage fluctuation. The LED module includes: a circuit board; a plurality of LED dies that are mounted on one surface of a circuit board as bare chips and constitute a series circuit; an FET die that is mounted on the one surface of a circuit board as bare chips and controls a current flowing through the plurality of LED dies; and a constant current circuit that is mounted on the one surface of a circuit board and is series-connected to the series circuit. The constant current circuit includes the FET die.

Abstract: A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate.

Abstract: An imaging apparatus includes: a lens group formed of one or more lens elements; and an imaging device having a light receiving surface on which the lens group forms an image of an object, wherein the light receiving surface of the imaging device is a curved surface that is concave toward the lens group, and the light receiving surface of the imaging device has an aspheric shape so shaped that a tangential angle that is an angle between a tangential line circumscribing an edge of the light receiving surface and a plane perpendicular to an optical axis of the lens group is smaller than the tangential angle provided when the light receiving surface has a spherical shape.

Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure.

Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.

Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.

Abstract: Measures are provided which are used for stabilizing the substructure of the connecting areas of ASIC elements. These measures relate to ASIC elements including an ASIC substrate, into which electrical circuit functions are integrated, and including an ASIC layer structure on the ASIC substrate, which includes multiple wiring levels for the circuit functions, which are separated from one another by insulation layers and are interconnected via metallic plugs. At least one connecting area for placing wire bonds or for wafer bonding is implemented in at least one of the uppermost wiring levels. At least one chain of metallic plugs arranged vertically in a direct line is implemented in the ASIC layer structure below the connecting area, which extends from the uppermost wiring level up to the ASIC substrate or oxide trenches introduced therein.

Abstract: A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined in the isolation layer; a fin region formed under the first trench; and a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches. The buried gate electrode includes a first work function layer formed on the sidewalls of the fin region; a second work function layer formed on sidewalls of the first trench and the second trench; a third work function layer positioned over the fin region and contacting the second work function layer; and a low resistance layer contacting the third work function layer and partially filling the first and second trenches.

Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer which each have a shape whose end portions are located on an inner side than end portions of the semiconductor layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is provided between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected in an opening provided in a gate insulating layer through an oxide conductive layer.

Abstract: A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.

Abstract: A semiconductor device includes: a semiconductor substrate; a high-voltage first resistive structure which extends along a spiral path above the substrate and is separated from the substrate by a first dielectric layer; and a conductive shielding structure, including a plurality of first shielding strips, which are arranged in sequence along respective portions of the first resistive structure and are separated from the first resistive structure by a second dielectric layer.

Abstract: This invention provides a high-efficiency light-emitting device and the manufacturing method thereof The high-efficiency light-emitting device includes a substrate; a reflective layer; a bonding layer; a first semiconductor layer; an active layer; and a second semiconductor layer formed on the active layer. The second semiconductor layer includes a first surface having a first lower region and a first higher region.

Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein, and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. Wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.

Abstract: An ultraviolet light emitting device having high quality and high reliability is provided by preventing deterioration of electrical characteristics which is associated with an ultraviolet light emission operation and caused by a sealing resin. The ultraviolet light emitting device is an ultraviolet light emitting device including: an ultraviolet light emitting element (2) formed of a nitride semiconductor; and an ultraviolet-transparent sealing resin (3) covering the ultraviolet light emitting element (2), wherein at least a specific portion (3a) of the sealing resin (3), which is in contact with pad electrodes (18) and (17) of the ultraviolet light emitting element (2), is a first type amorphous fluororesin, and a terminal functional group of a polymer or a copolymer that forms the first type amorphous fluororesin is a nonreactive terminal functional group which is not bondable to a metal that forms the pad electrodes (16) and (17).