Abstract: A process for the drying, and subsequent imidization, of polyimide precursors which minimizes or eliminates voids and which minimizes or eliminates discoloration. The process uses a sequential set of descending pressure operations that allow for time efficient processing of wafers. The set of descending pressure operations are interspersed with evacuation processes using heated gasses, which combine heating and byproduct evacuation. The process results in layers with reduced or eliminated voiding, discoloration, and solvent retention.

Abstract: A photosensor substrate achieves TFT property stabilization and further improvement in sensor performance. The photosensor substrate includes a substrate 7, a photoelectric transducer 4, and a transistor 2. The transistor 2 includes a semiconductor layer 22, a drain electrode 23 and a source electrode 21 facing each other in a direction parallel to a plane of the substrate with the semiconductor layer 22 interposed therebetween, a gate insulating film 15 covering the semiconductor layer 22, the drain electrode 23, and the source electrode 21, and a gate electrode 24 facing the semiconductor layer 22 with the gate insulating film 15 interposed therebetween. The photoelectric transducer 4 includes a lower electrode 41 connected to the drain electrode 23 via a contact hole CH1 provided in the gate insulating film 15, a semiconductor film 42, and an upper electrode 43.

Abstract: A preparation method of a conductive via hole structure, a preparation method of an array substrate and a preparation method of a display device, the preparation method of the array substrate includes: forming a first metal layer (01) including the first metal structure (01a), forming a non-metallic film including a first part corresponding to the first metal structure (01a) and an organic insulating film (40?) in sequence; patterning the organic insulating film (40?) to form a first organic insulating layer via hole (41) corresponding to the first part; then baking to form an organic insulating layer (40); and then, removing the first part of the non-metallic film to form a non-metallic layer and expose the part of the surface (011) of the first metal structure (01a). This method can avoid the metal structure from being seriously oxidized.

Abstract: A light-emitting element includes: a sapphire substrate including: a principal surface that is in a c-plane of the sapphire substrate, and a plurality of projections on the principal surface, wherein each of the plurality of projections has a shape of pseudo-hexagonal pyramid including six lateral surfaces, each of the six lateral surfaces including an inwardly curved surface portion, and wherein, in a top view of the sapphire substrate, each of the plurality of projections has a shape of a pseudo-hexagon; and a semiconductor layered body comprising a nitride semiconductor on the principal surface side of the sapphire substrate, the semiconductor layered body including an active layer.

Abstract: A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A metallic plated hole can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.

Abstract: A SOI substrate is covered by a semiconductor material pattern which includes a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which is facing the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a cap layer. The substrate is eliminated to access the source/drain regions. Two delineation patterns are formed to cover the source region and drain region and to leave the dividing pattern free. A second cap layer is deposited and access vias are formed to access the source/drain regions by elimination of the delineation patterns.

Abstract: An RC-IGBT has a chip area of the semiconductor chip larger than that of a semiconductor chip including an IGBT section but not including an FWD section, as it is provided with the FWD section. It is demanded to reduce the chip area of the RC-IGBT semiconductor chip. Provided is a semiconductor device including: a transistor section including a plurality of transistors; a free wheeling diode section being at least opposite to one side of the transistor section and provided outside the transistor section, when the transistor section is seen from a top view; and a gate runner section and a gate pad section provided to contact the transistor section and not surrounding an entire periphery of the transistor section, when the transistor section is seen from a top view.

Abstract: First, a substrate with one main surface on which a thin film of at least one of a mono-molecular layer and a multi-molecular layer including dopants is formed is prepared. Subsequently, the prepared substrate is placed in a chamber, and dopants included in the thin film are introduced from the thin film into a surface layer of the substrate by providing the substrate, through irradiation with light from a first lamp, with preliminary heat treatment in a first temperature band higher than a temperature before heating. Then, the dopants introduced into the surface layer of the substrate are activated by heating the substrate provided with the preliminary heat treatment and placed in the chamber from the first temperature band to a second temperature band higher than the first temperature band through irradiation with flash light from a second lamp.

Abstract: Embodiments of inventive concepts disclosed provide a method of manufacturing a semiconductor package. The method includes mounting a plurality of semiconductor chips on a substrate having a connecting member protruding from a top surface of the substrate, applying a non-conductive paste on the substrate and the semiconductor chips, forming a supporting layer coupling each of the semiconductor chips to the substrate, aligning an interposer on the non-conductive paste, forming a non-conductive layer by applying heat while pressing the interposer and the substrate against each other, and cutting the substrate, the non-conductive layer, and the interposer into separate unit packages, each of which include a semiconductor chip.

Abstract: A display apparatus includes a driving substrate, a plurality of light-emitting devices, and a plurality of metal common electrodes. The light-emitting devices are dispersedly disposed on the driving substrate, and each of the light-emitting devices includes an epitaxial structure and a first type electrode and a second type electrode disposed on the epitaxial structure. The metal common electrodes are dispersedly disposed on the driving substrate and in contact with a portion of the second type electrode of each of the light-emitting devices to form an ohmic contact.

Abstract: A communication device includes at least one radio that comprises signal processing circuitry, and at least one antenna coupled to the signal processing circuitry to send and receive radio signals. A component of the communication device requires user visibility and includes an isolator for isolating the at least one antenna, the isolator comprising at least one film that includes a transparent conductor. The component that requires user visibility may be a display screen or part of the chassis of a transparent communication device. The transparent conductor comprises a transparent conducting oxide such as indium tin oxide, indium tin oxide ink, graphite material, carbon nanotubes, or a conductive polymer.

Abstract: In a substrate processing apparatus, a mounting table and a gas supply part are provided in a processing container to face each other. The processing gas introduced from introduction ports formed in the gas supply part on the opposite side of the gas supply part from the mounting table is supplied to the substrate from gas supply holes formed in an end portion of the gas supply part on the side of the mounting table. The gas supply part includes a central region and one or more outer peripheral regions surrounding the central region. The gas supply holes and the introduction ports are provided for each of the central region and the outer peripheral regions. The processing gas whose gas supply conditions are adjusted for each of the regions is continuously and outwardly supplied in a circumferential direction around the center axis from the introduction ports.

Abstract: The present disclosure describes a sealing processes and structure for sealing air cavity electronic packages using a thermosetting, thermal plastic, other known or as yet unknown adhesives, or hybrid combinations of such adhesive(s). Processes disclosed comprise steps of providing a base and a lid, with at least one of the base and the lid having a mating surface coated with the adhesive. Initially, an air gap is maintained between the base, the lid, and the adhesive and a vacuum is generated around the base, the lid, and the adhesive. Once the vacuum has been generated, the base and the lid are mated to create a mated package assembly with a vacuum therein. After the mating, the mated package assembly is heated to a curing temperature to cure the adhesive, and pressure may be applied as well. Because the air within the mated package assembly has been evacuated prior to heating, there is no air pressure build-up therein, reducing or eliminating the presence of blowouts and pin holes.

Abstract: Provided is a material composition and method for that includes forming a silicon-based resin over a substrate. In various embodiments, the silicon-based resin includes a nitrobenzyl functional group. In some embodiments, a baking process is performed to cross-link the silicon-based resin. Thereafter, the cross-linked silicon-based resin is patterned and an underlying layer is etched using the patterned cross-linked silicon-based resin as an etch mask. In various examples, the cross-linked silicon-based resin is exposed to a radiation source, thereby de-cross-linking the silicon-based resin. In some embodiments, the de-cross-linked silicon-based resin is removed using an organic solution.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. Furthermore the present disclosure provides a photovoltaic device and a light emitting diode manufactured in accordance with the method. The method comprises the steps of forming a germanium layer using deposition techniques compatible with high-volume, low-cost manufacturing, such as magnetron sputtering, and exposing the germanium layer to laser light to reduce the amount of defects in the germanium layer. After the method is performed the germanium layer can be used as a virtual germanium substrate for the growth of III-V materials.

Abstract: A method for bonding a first substrate with a second substrate at respective contact faces of the substrates with the following steps: holding the first substrate to a first sample holder surface of a first sample holder with a holding force FH1 and holding the second substrate to a second sample holder surface of a second sample holder with a holding force FH2; contacting the contact faces at a bond initiation point and heating at least the second sample holder surface to a heating temperature TH; bonding of the first substrate with the second substrate along a bonding wave running from the bond initiation point to the side edges of the substrates, wherein the heating temperature TH is reduced at the second sample holder surface during the bonding.

Abstract: A light emitting package includes a first lead frame; a second lead frame spaced apart from the first lead frame in a first direction; a body coupled to the first lead frame and the second lead frame; and a light emitting element on the first lead frame. The first lead frame includes first to fourth side parts, the first side part includes a first protrusion that protrudes outwards from one side surface of the body, and a first contact part disposed at the end of the first protrusion. The second lead frame includes fifth to eighth side parts, the fifth side part includes a second protrusion that protrudes outwards from a side surface of the body, which is symmetrical to the one side surface of the body, and a second contact part disposed at the end of the second protrusion. Each of the first contact part and the second contact part includes a second layer and first layer covers the second layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer over a semiconductor substrate. The semiconductor device structure also includes a first conductive feature in the dielectric layer. A portion of the dielectric layer has a top surface that is provided on a different level in relation to a top surface of the first conductive feature. The semiconductor device structure further includes a second conductive feature in the dielectric layer and extending from a bottom surface of the first conductive feature. The portion of the dielectric layer is separated from the second conductive feature by a gap. A distance between the portion of the dielectric layer and the second conductive feature becomes smaller along a direction from the top surface of the first conductive feature towards the bottom surface of the first conductive feature.

Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.

Abstract: An ion implantation system is provided having an ion source configured to form an ion beam from aluminum iodide. A beamline assembly selectively transports the ion beam to an end station configured to accept the ion beam for implantation of aluminum ions into a workpiece. The ion source has a solid-state material source having aluminum iodide in a solid form. A solid source vaporizer vaporizes the aluminum iodide, defining gaseous aluminum iodide. An arc chamber forms a plasma from the gaseous aluminum iodide, where arc current from a power supply is configured to dissociate aluminum ions from the aluminum iodide. One or more extraction electrodes extract the ion beam from the arc chamber. A water vapor source further introduces water to react residual aluminum iodide to form hydroiodic acid, where the residual aluminum iodide and hydroiodic acid is evacuated from the system.