Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.

Abstract: A method of processing a wafer having a metal film formed on a reverse side thereof includes removing a metal film on the reverse side of the wafer along an outer circumferential edge of the wafer, thereby exposing a substrate of the wafer along the outer circumferential edge thereof, detecting a projected dicing line on a face side of the wafer with an infrared camera through the substrate exposed along the outer circumferential edge of the wafer and performing alignment of the wafer based on the detected projected dicing line, removing the metal film on the reverse side of the wafer along the detected projected dicing line, and thereafter, forming dividing grooves in the substrate along the projected dicing lines by plasma etching, thereby dividing the wafer into individual device chips.

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

Abstract: Various systems, devices and methods are provided for interconnection between wafers and/or chips using catch flexures. In one example, among others, a catch flexure assembly includes a first interconnect affixed to a first wafer. The first interconnect can include a female opening at a distal end of a flexible member that is configured to receive a male extension of a second interconnect affixed to a second wafer when the first wafer is aligned with the second wafer, and retain the male extension during a bonding process of the first and second flexible interconnects. The catch flexure assembly can also include bonding material disposed adjacent to the female opening, which is configured to secure the male extension in the female opening during the bonding process.

Abstract: A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A PMOS FinFET device includes a second fin. The second fin includes a second strain relaxed buffer layer and a second channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A first gate structure is positioned around a portion of the NMOS fin. A second gate structure is positioned around a portion of the PMOS fin.

Abstract: A semiconductor device includes a resistive element wherein a diffusion resistance region provided in an upper portion of a semiconductor base and a thin film resistance layer isolated and distanced from the semiconductor base and diffusion resistance region across an insulating film are alternately connected in series and alternately disposed in parallel.

Abstract: Semiconductor devices including super via structures and BEOL processes for forming the same, according to embodiments of the invention, generally include removing selected portions of a nitride cap layer intermediate interconnect levels, wherein the selected portions correspond to the regions where the super via structure is to be formed and where underlying overlay alignment markers are located.

Abstract: Semiconductor devices including super via structures and BEOL processes for forming the same, according to embodiments of the invention, generally include removing selected portions of a nitride cap layer intermediate interconnect levels, wherein the selected portions correspond to the regions where the super via structure is to be formed and where underlying overlay alignment markers are located.

Abstract: Device structures and fabrication methods for an on-chip resistor. A first Seebeck terminal is arranged to overlap with first and second resistor bodies of the on-chip resistor. A second Seebeck terminal is also arranged to overlap with the first and second resistor bodies. The second Seebeck terminal has a spaced relationship with the first Seebeck terminal along a length of the first and second resistor bodies. The temperature coefficient of resistance of the on-chip resistor is based at least in part on a Seebeck coefficient of first and second Seebeck terminals.

Abstract: The present disclosure relates a method for transfer printing of an electronic device comprising: forming a sacrificial layer on a handling substrate; forming a protective layer on the sacrificial layer; forming a polymer substrate on the protective layer; forming a pattern on the polymer substrate, and forming a ciliary adhesive rod on the sides of the polymer substrate; forming a supportive layer on the polymer substrate on which the adhesive rod is formed; and removing the sacrificial layer and the protective layer, and transfer printing the electronic device onto an object to-be-printed, while dissolving the to supportive layer.

Abstract: A compound semiconductor device disclosed herein includes: a substrate; an electron transit layer formed on the substrate and made of nitride semiconductor doped with an impurity that forms a trap level; a barrier layer formed on the electron transit layer; and a source electrode, a drain electrode, and a gate electrode formed over the electron transit layer at a distance from one another, wherein the electron transit layer includes: a first conductivity type region; a second conductivity type region located over the first conductivity region, where the second conductivity type region having an electron concentration higher than an electron concentration of the first conductivity type region; and a third conductivity type region located over the second conductivity type region, where the third conductivity type region having an electron concentration lower than a concentration of the impurity and being in contact with an upper surface of the electron transit layer.

Abstract: The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract: Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal particle-containing precursor layer over a first principal surface of a first metal layer. The first metal layer and the metal particle-containing layer are then arranged in a stacked relationship with a second metal layer such that the precursor layer is disposed between the first and second metal layers. A low temperature sintering process is then carried-out at a maximum process temperature less than a melt point of the metal particles to transform the precursor layer into a sintered bond layer joining the first and second metal layers in a sintered multilayer heat sink. In embodiments wherein the sintered multilayer heat sink is contained within a heat sink panel, singulation may be carried-out to separate the sintered multilayer heat sink from the other heat sinks within the panel.

Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.

Abstract: Methods and structures for forming flat, continuous, planar, epitaxial layers of semipolar III-nitride materials on patterned sapphire substrates are described. Semipolar GaN may be grown from inclined c-plane facets on a patterned sapphire substrate, and coalesced to form a continuous layer of semipolar III-nitride semiconductor over the sapphire substrate. Planarization of the layer is followed by crystal regrowth using a nitrogen carrier gas to produce a flat, microfabrication-grade, process surface of semipolar III-nitride semiconductor across the substrate. Quality multiple quantum wells can be fabricated in the regrown semipolar material.

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

Abstract: A high-performance semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a first metal oxide covering at least part of the first transistor, an insulating film over the first transistor and the second transistor, and a second metal oxide over the insulating film. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide, a first source electrode, a first drain electrode, a second gate insulating film, and a second gate electrode. The second transistor includes a third gate electrode, a third gate insulating film, a second oxide, a second source electrode, a second drain electrode, a fourth gate insulating film, and a fourth gate electrode. The first gate insulating film and the second gate insulating film are in contact with the first metal oxide.

Abstract: A light-emitting element includes a sapphire substrate including: a principal surface that is in a c-plane of the sapphire substrate, and a plurality of projections on the principal surface, wherein each of the plurality of projections has a shape of pseudo-hexagonal pyramid including six lateral surfaces, each of the six lateral surfaces including an inwardly curved surface portion, and wherein, in a top view of the sapphire substrate, each of the plurality of projections has a shape of a pseudo-hexagon that includes first curved lines and second curved lines that are alternately connected to one another, the first curved lines being curved toward a center of a corresponding hexagon and disposed between respective adjacent pairs of six vertices of the hexagon, and the second curved lines passing through respective vertices of the hexagon; and a semiconductor layered body comprising a nitride semiconductor on the principal surface side of the sapphire substrate, the semiconductor layered body including an act