Abstract: A method of manufacturing an organic EL display unit and an organic EL display unit capable of improving light emitting efficiency and life of blue are provided. A hole injection layer are formed on a lower electrode. For a red organic EL device and a green organic EL device, a hole transport layer, a red light emitting layer, and a green light emitting layer made of a polymer material are formed. A hole transport layer made of a low molecular material is formed on the hole injection layer of a blue organic EL device. A blue light emitting layer made of a low molecular material is formed on the red light emitting layer, the green light emitting layer, and the hole transport layer for the blue organic EL device. An electron transport layer, an electron injection layer, and an upper electrode are sequentially formed on the blue light emitting layer.

Abstract: The present invention discloses a lighting emitting diode device with directivity and coherency and a manufacturing method for providing a light with directivity and coherency. The light emitting diode device comprises a substrate, a light emitting diode module and a masking layer. The light emitting diode module is disposed on the substrate, and is provided for emitting a light, and the masking layer is disposed on the light emitting diode module. The masking layer has an opening, and an aperture of the opening is matching with the wavelength of the light. The light with directivity and coherency is generated by the diffraction effect when the light passes through the opening.

Abstract: A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.

Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

Abstract: The electroluminescence element comprises the light-reflective-electrode separated from the luminous point by distance “d” satisfying the following formula. nd = a × ? 4 ? { 2 ? m + ? ? } ? ? wherein ? ? ? = tan - 1 ? { 2 ? ( n 1 ? k 2 - n 2 ? k 1 ) n 1 2 - n 2 2 + k 1 2 - k 2 2 } ? is a wavelength of the light from the light emission layer. N is a refractive index of a certain layer between the luminous point and the light-reflective-electrode at ?. n1 and k1 is a refractive index and the extinction coefficient of the certain layer at ?. n2 and k2 is a refractive index and the extinction coefficient of the light-reflective-electrode at ?. m is 0 or 1. When “m” is 0, “a” satisfies the following formula. ?1.17×norg/nEML+1.94?a??0.16×norg/nEML+2.33 When “m” is 1, “a” satisfies the following formula. 0.28×norg/nEML+0.75?a?2.85×norg/nEML?1.

Abstract: A chip stack package is provided. The chip stack package includes an n number of chips stacked on each other and an n number of interconnection strands connecting the chips. The interconnection strands are spirally rotated and insulated from each other. In one embodiment, the chips are substantially structurally identical. In another embodiment, each of the interconnection strands is electrically coupled to a chip selection signal.

Abstract: A semi-conductor light emitting device 10 in the present invention comprises an n-type ZnO substrate 3, an emission layer 2, anode 5, and cathode 4. The n-type ZnO substrate 3 has a mounting surface 31 on one of its surfaces. The emission layer 2 is composed of a p-type GaN film 24 and an n-type GaN film 22, and superimposed on the n-type ZnO substrate 3 with the p-type GaN film 24 directly disposed on the mounting surface 31 of the n-type ZnO substrate 3. The anode 5 is disposed directly on the mounting surface 31 of the n-type GaN substrate 3 in an ohmic contact therewith and in a spaced relation from the emission layer. The cathode 4 is disposed on the n-type GaN film 22 in an ohmic contact therewith. The cathode 4 and anode 5 are of the same structure solely composed of a metallic material. The semi-conductor light emitting device in the present invention assures good ohmic contact of both the cathode 4 and the anode 5, and minimizes consumption of metallic materials.

Abstract: A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.

Abstract: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film.

Abstract: A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Abstract: This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

Abstract: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged in a two-dimensional array, in which the imaging region includes an effective pixel and a black reference pixel; and a shape of a floating diffusion portion in the effective pixel is different from that of a floating diffusion portion in the black reference pixel.

Abstract: A die structure and a die connecting method using the same are provided. The die structure includes a die and a bump structure. The bump structure includes a body and a solder layer. The body is disposed on the die. The solder layer is disposed on the body. The method includes providing a die structure mentioned above, providing a circuit board mentioned above, and soldering the solder layer of the die structure with the tine layer on the copper block of the circuit board. In different embodiments, a tin layer is omitted from the circuit board, wherein the solder layer of the die structure is directly soldered onto the surface of the copper block.

Abstract: An exemplary embodiment of a non-volatile memory includes a bottom conductive layer, a resistive switching layer, an oxygen vacancy barrier layer and an upper conductive layer. The resistive switching layer is disposed on the bottom conductive layer. The oxygen vacancy barrier layer is disposed on the resistive switching layer. The upper conductive layer is disposed on the oxygen vacancy barrier layer.

Abstract: An image sensor having an array of pixels disposed in a substrate. The array of pixels includes photosensitive elements, a color filters, and waveguide walls. The waveguide walls are disposed in the color filters and surround portions of the color filters to form waveguides through the color filters. In some embodiments, metal walls may be coupled to the waveguide walls.

Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are disclosed.

Abstract: Provided is a III nitride semiconductor electronic device having a structure capable of reducing leakage current. A laminate 11 includes a substrate 13 and a III nitride semiconductor epitaxial film 15. The substrate 13 is made of a III nitride semiconductor having a carrier concentration of more than 1×1018 cm?3. The epitaxial structure 15 includes a III nitride semiconductor epitaxial film 17. A first face 13a of the substrate 13 is inclined at an angle ? of more than 5 degrees with respect to an axis Cx extending in a direction of the c-axis. A normal vector VN and a c-axis vector VC make the angle ?. The III nitride semiconductor epitaxial film 17 includes first, second and third regions 17a, 17b and 17c arranged in order in a direction of a normal to the first face 13a. A dislocation density of the third region 17c is smaller than that of the first region 17a. A dislocation density of the second region 17b is smaller than that of the substrate 13.

Abstract: A memory device includes an array of electrodes that includes thin film plates of electrode material. Multilayer strips are arranged as bit lines over respective columns in the array of electrodes, including a layer of memory material and a layer of top electrode material. The multilayer strips have a primary body and a protrusion having a width less than that of the primary body and is self-aligned with contact surfaces on the thin film plates. Memory material in the protrusion contacts surfaces on the distal ends of thin film plates of electrodes in the corresponding column in the array. The device can be made using a damascene process in self-aligned forms over the contact surfaces.

Abstract: In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115).

Abstract: The invention relates to a contact structure (24) and to a method for producing a contact structure for semiconductor substrates (21) or the like, in particular for terminal faces of semiconductor substrates, comprising a base contact part (22) arranged on a terminal face (20) of the semiconductor substrate and at least one connecting contact part (23) arranged on the base contact part, wherein the connecting contact part is formed from a connecting contact material (34) which has a lower melting point than a base contact material of the base contact part.