Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A multi-chip module (MCM) includes a common substrate and first and second integrated circuit (IC) chips disposed on the common substrate. The first integrated circuit (IC) chip includes a first interface circuit disposed proximate a first edge of the first IC chip and a second interface circuit disposed proximate the first edge of the first IC chip. A first chiplet couples to the first interface circuit via a first link. A second chiplet couples to the second interface circuit via a second link. A first position of the first chiplet with respect to the first IC chip is staggered in a longitudinal dimension relative to a second position of the second chiplet with respect to the first IC chip.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: The invention relates to a method (110) for producing an electrically conductive connection (112, 112?) on a substrate (114), comprising the following steps: a) providing a substrate (114), wherein the substrate (114) is configured for receiving an electrically conductive connection (112, 112?); b) providing a reservoir of an electrically conductive liquid alloy, wherein the reservoir has a surface at which the alloy has an insulating layer; c) providing a capillary (120) configured for taking up the electrically conductive liquid alloy; d) penetrating of a tip (122) of the capillary (120) under the surface of the reservoir and taking up of a portion of the alloy from the reservoir; and e) applying the portion of the alloy at least partly to the substrate (114) in such a manner that an electrically conductive connection (112, 112?) is formed from the alloy on the substrate (114), wherein the alloy remains on the substrate (114) by adhesion.

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.

Abstract: A sensor includes an anode and a cathode, and a near-infrared photoelectric conversion layer between the anode and the cathode. The near-infrared photoelectric conversion layer is configured to absorb light of at least a portion of a near-infrared wavelength spectrum and convert the absorbed light into an electrical signal. The near-infrared photoelectric conversion layer includes a first material having a maximum absorption wavelength in the near-infrared wavelength spectrum and a second material forming a pn junction with the first material and having a wider energy bandgap than an energy bandgap of the first material. The first material is included in the near-infrared photoelectric conversion layer in a smaller amount than the second material.

Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

Abstract: A method includes arranging a substrate in a processing chamber, and exposing the substrate to a gas mixture including a first metal precursor gas and a second metal precursor gas to deposit a first metal precursor and a second metal precursor onto the substrate at the same time. The method further includes purging the processing chamber, supplying a reactant common to both the first metal precursor and the second metal precursor to form a layer of an alloy on the substrate, and purging the processing chamber.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation feature over the semiconductor substrate, a fin protruding from the semiconductor substrate and through the isolation feature, a gate stack over and engaging the fin, and a gate spacer on sidewalls of the gate stack. A bottom portion of the sidewalls of the gate stack tilts inwardly towards the gate stack.

Abstract: In an embodiment, a method for manufacturing a semiconductor device includes forming a redistribution structure on a carrier substrate, connecting a plurality of core substrates physically and electrically to the redistribution structure with a first anisotropic conductive film, the first anisotropic conductive film including a dielectric material and conductive particles, and pressing the plurality of core substrates and the redistribution structure together to form conductive paths between the plurality of core substrates and the redistribution structure with the conductive particles in the first anisotropic conductive film. The method also includes encapsulating the plurality of core substrates with an encapsulant.

Abstract: An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.

Abstract: There is provided a method of filling one or more recesses by providing the substrate in a reaction chamber; introducing a first reactant, to form first active species, for a first pulse time to the substrate; introducing a second reactant for a second pulse time to the substrate; and introducing a third reactant, to form second active species, for a third pulse time to the substrate. An apparatus for filling a recess is also disclosed and a structure formed using the method and/or apparatus is disclosed.

Abstract: A package structure includes a circuit substrate, a semiconductor device and a ring structure. The circuit substrate has a first region and a second region connected thereto. The circuit substrate includes at least one routing layer including a dielectric portion and a conductive portion disposed thereon. A first ratio of a total volume of the conductive portion of the routing layer within the first region to a total volume of the dielectric and conductive portions of the routing layer within the first region is less than a second ratio of a total volume of the conductive portion of the routing layer within the second region to a total volume of the dielectric and conductive portions of the routing layer within the second region. The semiconductor device is disposed over the circuit substrate within the first region, and is electrically coupled to the circuit substrate. The ring structure is disposed over the circuit substrate within the second region.

Abstract: An electrical power assembly, comprising: at least one multilayer base structure, at least one power device embedded in the at least one multilayer base structure, an internal electrically conductive layer positioned on each side of the multilayer base structure, the internal electrically conductive layer being connected to a respective electrical contact of the power device through connections arranged in the multilayer base structure; at least one external electrically conductive layers positioned on each side of the base structure, each external electrically conductive layer comprising at least one pre-drilled through hole, at least one internal electrically insulating layer positioned between the internal electrically conductive layer of the base structure and a respective external electrically conductive layer, at least one hole arranged in the internal electrically insulating layer and the external electrically conductive layer, a portion of each hole being formed by the pre-drilled through hole, the at

Abstract: A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

Abstract: A semiconductor package includes a package substrate, a connection substrate on the package substrate, a first image sensor chip on the connection substrate, a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip, and a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate. A distance between the first image sensor chip and the second image sensor chip is less than a thickness of the first image sensor chip.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

Abstract: A semiconductor package may include a semiconductor chip including a chip pad, a redistribution structure including a redistribution insulation layer on the semiconductor chip and first redistribution patterns on a surface of the redistribution insulation layer, a passivation layer covering the first redistribution patterns, an UBM pattern on the passivation layer and extending into an opening of the passivation layer, a second redistribution pattern on the UBM pattern, conductive pillars on the second redistribution pattern, and a package connection terminal on the conductive pillars. The opening in the passivation layer may vertically overlap a portion of each of the first redistribution patterns. The second redistribution pattern may connect some of the first redistribution patterns to each other. Some of the conductive pillars may be connected to one another through the second redistribution pattern. The first redistribution patterns may be connected to the chip pad.

Abstract: A high-frequency module includes a semiconductor element, a first insulating layer, an acoustic wave element, a second insulating layer, a first intermediate layer, and a second intermediate layer. The first intermediate layer is interposed between the acoustic wave element and the semiconductor element, and has a thermal conductivity lower than the first and second insulating layers. The second intermediate layer is interposed between the first insulating layer and the second insulating layer, and has a thermal conductivity lower than the first and second insulating layers. A step is provided between a first principal surface of the first insulating layer and one principal surface of the semiconductor element. The distance between first and second principal surfaces of the first insulating layer is greater than the distance between the second principal surface of the first insulating layer and the one principal surface of the semiconductor element.