Abstract: A one-to-many communication circuit includes a recommended standard 232 signal transceiver, a main controller area network transceiver, and a plurality of subordinate controller area network transceivers. The recommended standard 232 signal transceiver is used to receive a control signal from a main controller and convert the control signal into a first signal conforming to the recommended standard 232 communication protocol. The main controller area network transceiver is used to convert the first signal into a second signal conforming to the controller area network communication protocol. And each of the plurality of subordinate controller area network transceivers is used to convert the second signal into a third signal conforming to the recommended standard 232 communication protocol.

Abstract: A machine learning device including a general-purpose memory module interface is disclosed. The machine learning device includes a data storage circuit configured to store raw data and command data received from a host device through a memory module interface, and store machine learning data as a result of machine learning of the raw data and location data of the machine learning data, a machine learning logic circuit configured to generate the machine learning data through the machine learning of the raw data according to a pre-programmed machine learning logic, and a machine learning controller configured to read the raw data from the data storage circuit based on the command data, transmit the read raw data to the machine learning logic circuit, and write the machine learning data and the location data in the data storage circuit.

Abstract: Techniques for creating and establishing a configuration of connections between an initiator system and a target system can use whitelisted target ports, wherein the configuration only includes connections to selected whitelisted target ports. Automatic login of each initiator to all zoned and discovered target ports can be avoided where, alternatively, an on-demand or needs-based login can be performed by having each initiator only log into its whitelisted target ports. In this manner, better resource usage and scalability can be obtained using the techniques of the present disclosure. In one embodiment, the whitelisted target ports can be determined automatically using an intersection of target port lists obtained using a control path connection and using a fabric nameserver query. The configuration including the whitelisted targets can be persistently stored on the initiator system to enable restoration of the whitelisted targets across reboots and resets of the initiator system.

Abstract: Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.

Abstract: Methods and systems related to parallel computing using heterogeneous networks of computational nodes are disclosed herein. A method for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network is disclosed. The method includes compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for the execution of the complex computation. The method also includes configuring a set of programmable controllers on the heterogeneous set of computational nodes with the set of instructions. The method also includes executing the set of instructions using the set of programmable controllers. The method also includes routing data through the network to facilitate the execution of the complex computation by the heterogeneous set of computational nodes and in response to the execution of the instructions.

Abstract: A computer system and method for synchronizing actions associated with media between a media/network device and peripherals. In an example implementation, a system includes a one or more processors configured to receive, by a communication module from a media/network device based on peripheral addressing information, a peripheral payload including a first set of actions and timing information related to media. The one or more processors perform the first set of actions based on the peripheral payload, generate response data for the first set of actions, and transmit the response data to the media/network device via a wireless network.

Abstract: Data may be communicated from a sender device to a receiver device over enabled or selected byte positions or other data bit groups of a data bus. The sender device may determine data values to be sent over the data bus and may determine which byte positions are enabled or selected and which are not selected. The sender device may also determine a code. The code may be a value that is not included in the data values to be sent over the data bus. The sender device may then send the selected data values in selected byte positions of the data bus and send the code in non-selected byte positions of the data bus. The sender device may also send the code to the receiver device separately from the data bit lanes of the data bus.

Abstract: Disclosed is a data processing system to receive a processing graph of an application. A compile time logic is configured to modify the processing graph and generate a modified processing graph. The modified processing graph is configured to apply a post-padding tiling after applying a cumulative input padding that confines padding to an input. The cumulative input padding pads the input into a padded input. The post-padding tiling tiles the padded input into a set of pre-padded input tiles with a same tile size, tiles intermediate representation of the input into a set of intermediate tiles with a same tile size, and tiles output representation of the input into a set of non-overlapping output tiles with a same tile size. Runtime logic is configured with the compile time logic to execute the modified processing graph to execute the application.

Abstract: A method of a memory device, a storage system, and a memory device are provided. The method includes receiving a set of entries, where the set of entries includes a first entry from a source queue and addressed to a first destination and a second entry addressed to a second destination, determining to add a third entry associated with the first entry and addressed to the first destination to the set of entries, selecting one of the first entry and the third entry as a restock entry and the other of the first entry and the third entry as a pass-through entry, sending the restock entry to the source queue, and sending the second entry and the pass-through entry to a serial link connected to the first destination and the second destination.

Abstract: An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.

Abstract: A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing elements in first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading elements in first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of low data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to High.

Abstract: The present invention relates to a bridge device operable between a master device and a slave device of a communication system, said master device and said slave device arranged for communicating with each other via a parent I2C bus and a child I2C bus and using the I2C protocol, said bridge device comprising—a parent module arranged for connecting said parent I2C bus and comprising a parent I2C transmitter/receiver device and a parent module state machine, —a child module arranged for connecting said child I2C bus and comprising a child I2C transmitter/receiver device and a child module state machine, whereby said parent module and said child module each comprise an internal bridge interface to exchange messages between said parent module and said child module, said messages being generated by said parent module state machine or said child module state machine in response to a change of state caused by an event on their respective I2C buses, whereby said parent module and said child module are each arranged

Abstract: Techniques for generating distributed representations of computing processes and events are provided. According to one set of embodiments, a computer system can receive occurrence data pertaining to a plurality of computing processes and a plurality of events associated with the plurality of computing processes. The computer system can then generate, based on the occurrence data, (1) a set of distributed process representations that includes, for each computing process, a representation that encodes a sequence of events associated with the computing process in the occurrence data, and (2) a set of distributed event representations that includes, for each event, a representation that encodes one or more event properties associated with the event and one or more events that occur within a window of the event in the occurrence data.

Abstract: Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.

Abstract: The present disclosure provides a processor array and a multiple-core processor. The processor array includes a plurality of processing elements arranged in a two-dimensional array, a plurality of first load units correspondingly arranged and connected to the processing elements of the first edge row, respectively, a plurality of second load units correspondingly arranged and connected to the processing elements of the first edge column, respectively, a plurality of first store units correspondingly arranged and connected to the processing elements of the second edge column, respectively, a plurality of second store units correspondingly arranged and connected to the processing elements of the second edge row, respectively.

Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes a first controller and a NAND package. The NAND package includes a plurality of dies grouped into a plurality of subsets. The NAND package includes a second controller operatively coupled to each of the plurality of subsets via a corresponding one of a plurality of parallel mode channels. The first controller is operatively coupled to the NAND package via a serial link.

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.

Abstract: An information handling system may include a processor, a display device communicatively coupled to the processor, and a basic input/output system (BIOS) communicatively coupled to the processor and configured to cause the processor to, during a pre-boot environment of the information handling system, collect contextual information regarding the information handling system, based on the contextual information, determine whether to enable soft keyboard functionality, and responsive to a determination to enable soft keyboard functionality, cause display of soft keyboard functionality to the display device.

Abstract: Techniques and apparatus for dynamically modifying a kernel (and associated user-specified circuitry) for a dynamic region of a programmable integrated circuit (IC) without affecting (e.g., while allowing) operation of other kernels ((and other associated user-specified circuitry) in the programmable IC. Dynamically modifying a kernel may include, for example, unloading an existing kernel, loading a new kernel, or replacing a first kernel with a second kernel). In the case of networking (e.g., in a data center application) where the programmable IC may be part of a hardware acceleration card (e.g., a network interface card (NIC)), the kernel may be user code referred to as a “plugin.