Patents Examined by Farley Abad
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Patent number: 11734012Abstract: According to one general aspect, a non-transitory computer readable medium includes instructions that, when executed by at least one processor, cause a computing device to read a string of a log file for an application, where the log file comprises multiple strings of log data, compare the string to signatures stored in a memory to find a matching signature, where each of the signatures is encoded with a signature identifier (ID), determine a deviation between the string and the matching signature, encode the string with the signature identifier (ID) of the matching signature and the deviation, and transfer the string to a destination computing device using the signature identifier (ID) of the matching signature, the deviation, and a timestamp of the string.Type: GrantFiled: March 31, 2021Date of Patent: August 22, 2023Assignee: BMC Software, Inc.Inventors: Rakesh Tiwari, Dasari Subramanyeswara Rao, Jatinkumar Jayantkumar Parikh
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Patent number: 11726932Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.Type: GrantFiled: June 14, 2021Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: George Chong Hean Ooi, Lai Guan Tang, Chee Hak Teh
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Patent number: 11714875Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.Type: GrantFiled: December 28, 2019Date of Patent: August 1, 2023Assignee: Intel CorporationInventors: Amit Gradstein, Simon Rubanovich, Sagi Meller, Saeed Kharouf, Gavri Berger, Zeev Sperber, Jose Yallouz, Ron Schneider
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Patent number: 11714773Abstract: An information handling system includes a processor that provides a USB-2 channel and a USB-3 channel to a device. The device provides the USB-2 and -3 channels to selected ports. Each port includes a USB-3 enable setting. When the USB-3 enable setting for each particular USB port is in a first state, the associated device USB-3 channel is active, and when the USB-3 enable setting for each particular USB port is in a second state, the associated device USB-3 channel is inactive. The USB-3 enable setting for at least one of the USB ports is placed into the second state to reduce electromagnetic interference between the associated USB-3 channel and an antenna.Type: GrantFiled: December 20, 2021Date of Patent: August 1, 2023Assignee: Dell Products L.P.Inventors: Richard Schaefer, Daniel W. Kehoe, Derric C. Hobbs
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Patent number: 11704545Abstract: Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.Type: GrantFiled: December 19, 2019Date of Patent: July 18, 2023Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITEDInventors: Shaoli Liu, Xinkai Song, Bingrui Wang, Yao Zhang, Shuai Hu
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Patent number: 11693691Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.Type: GrantFiled: July 21, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman, Niall D. McDonnell, Michael A. O'Hanlon, Lokpraveen B. Mosur, Tracy Garrett Drysdale, Eriko Nurvitadhi, Asit K. Mishra, Ganesh Venkatesh, Deborah T. Marr, Nicholas P. Carter, Jonathan D. Pearce, Edward T. Grochowski, Richard J. Greco, Robert Valentine, Jesus Corbal, Thomas D. Fletcher, Dennis R. Bradford, Dwight P. Manley, Mark J. Charney, Jeffrey J. Cook, Paul Caprioli, Koichi Yamada, Kent D. Glossop, David B. Sheffield
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Patent number: 11694650Abstract: An electronic apparatus includes: a signal output circuit configured to connect with an external apparatus connected to a display apparatus, a processor configured to control the electronic apparatus to: obtain information about a first image format supported in the display apparatus from the external apparatus, output a content signal having the first image format to the external apparatus through the signal output circuit to the display apparatus based on identifying that the external apparatus supports an interface protocol capable of transmitting the content signal having the first image format, and output a content signal having a second image format different from the first image format to the external apparatus through the signal output circuit based on identifying that the external apparatus does not support the interface protocol.Type: GrantFiled: October 14, 2021Date of Patent: July 4, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Sungbo Oh
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Patent number: 11694060Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a neural network that is configured to receive a network input and to generate a network output for the network input. The neural network comprises a plurality of layers arranged in a sequence, including a plurality of capsule layers. Each particular capsule in a particular capsule layer is configured to receive respective inputs including: (i) outputs generated by capsules of a previous capsule layer that is before the particular capsule layer in the sequence, and (ii) final routing factors between capsules of the previous capsule layer and the particular capsule, wherein the final routing factors are generated by a routing subsystem. Each particular capsule in the particular capsule layer is configured to determine a particular capsule output based on the received inputs, wherein the particular capsule output is of dimension greater than one.Type: GrantFiled: October 4, 2022Date of Patent: July 4, 2023Assignee: Google LLCInventors: Geoffrey E. Hinton, Nicholas Myles Wisener Frosst, Sara Sabour Rouh Aghdam
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Patent number: 11681543Abstract: A hypervisor virtual server system, including a plurality of virtual servers, a plurality of virtual disks that are read from and written to by the plurality of virtual servers, a physical disk, an I/O backend coupled with the physical disk and in communication with the plurality of virtual disks, which reads from and writes to the physical disk, a tapping driver in communication with the plurality of virtual servers, which intercepts I/O requests made by any one of said plurality of virtual servers to any one of said plurality of virtual disks, and a virtual data services appliance, in communication with the tapping driver, which receives the intercepted I/O write requests from the tapping driver, and that provides data services based thereon.Type: GrantFiled: June 24, 2021Date of Patent: June 20, 2023Inventor: Ziv Kedem
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Processing unit and method for computing a convolution using a hardware-implemented spiral algorithm
Patent number: 11669733Abstract: Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N×N activations matrix) and a weights kernel (e.g., a M×M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.Type: GrantFiled: December 23, 2019Date of Patent: June 6, 2023Assignee: Marvell Asia Pte. Ltd.Inventors: Deepak I. Hanagandi, Venkatraghavan Bringivijayaraghavan, Aravindan J. Busi -
Patent number: 11656909Abstract: A tensor accelerator includes two tile execution units and a bidirectional queue. Each of the tile execution units includes a buffer, a plurality of arithmetic logic units, a network, and a selector. The buffer includes a plurality of memory cells. The network is coupled to the plurality of memory cells. The selector is coupled to the network and the plurality of arithmetic logic units. The bidirectional queue is coupled between the selectors of the tile execution units.Type: GrantFiled: April 15, 2021Date of Patent: May 23, 2023Assignee: National Taiwan UniversityInventors: Shao-Yi Chien, Yu-Sheng Lin, Wei-Chao Chen
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Patent number: 11650794Abstract: An electronic control apparatus includes a first arithmetic processor and a second arithmetic processor that is communicably connected to the first arithmetic processor. The second arithmetic processor includes a controller configured to (i) shift to a rewriting wait state after outputting a request signal that requests a program rewriting to the first arithmetic processor, and (ii) release the rewriting wait state and shift to a program rewriting process after a predetermined wait time that allows the first arithmetic processor to shift to the program rewriting process elapses after outputting the request signal.Type: GrantFiled: March 4, 2021Date of Patent: May 16, 2023Assignee: DENSO TEN LimitedInventors: Dongliang Fan, Hironori Yohata, Shigeto Umeyama
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Patent number: 11650953Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.Type: GrantFiled: October 16, 2020Date of Patent: May 16, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
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Patent number: 11650842Abstract: A cross-host multi-hypervisor system, including a plurality of host sites, each site including at least one hypervisor, each of which includes at least one virtual server, at least one virtual disk that is read from and written to by the at least one virtual server, a tapping driver in communication with the at least one virtual server, which intercepts write requests made by any one of the at least one virtual server to any one of the at least one virtual disk, and a virtual data services appliance, in communication with the tapping driver, which receives the intercepted write requests from the tapping driver, and which provides data services based thereon, and a data services manager for coordinating the virtual data services appliances at the site, and a network for communicatively coupling the plurality of sites, wherein the data services managers coordinate data transfer across the plurality of sites via the network.Type: GrantFiled: February 2, 2022Date of Patent: May 16, 2023Inventors: Ziv Kedem, Chen Yehezkel Burshan, Yair Kuszpet, Gil Levonai
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Patent number: 11651064Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.Type: GrantFiled: March 27, 2020Date of Patent: May 16, 2023Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael Peeters, Fabrice Marinet
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Patent number: 11645075Abstract: Execution flows of a program can be characterized by a series of execution events. The rates at which these execution events occur for a particular program can be collected periodically, and the execution events statistics can be utilized for both training a machine learning model, and later on for making classification inferences to determine whether a program run contains any abnormality. When an abnormality is encountered, an alert can be generated and provided to supervisory logic of a computing system to indicate that an abnormal program flow has been detected.Type: GrantFiled: June 30, 2021Date of Patent: May 9, 2023Assignee: Amazon Technologies, Inc.Inventors: Barak Wasserstrom, Adi Habusha, Ron Diamant, Erez Sabbag
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Patent number: 11630748Abstract: Methods and systems for operating internal systems of a vehicle are provided. Aspects include providing a field programmable gate array (FPGA), the FPGA including a communication channel port, wherein the communication channel port is operable to connect to one or more systems through a communication channel, and wherein the FPGA is configured to operate in one or more control modes, receiving a communication channel input to the communication channel port of the FPGA, based at least in part on the communication channel input, determining a control mode from the one or more control modes, and operating the FPGA in the control mode, wherein the control mode is associated with one system of the one or more systems.Type: GrantFiled: March 27, 2019Date of Patent: April 18, 2023Assignee: HAMILTON SUNDSTRAND CORPORATIONInventors: Robert P. Wichowski, Timothy A. Roberts, Patrick J. Sears
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Patent number: 11625605Abstract: Apparatuses, systems, and techniques to optimize kernel selection for performing a computation. In at least one embodiment, a neural network is trained and utilized to generate a list of kernels so that an (e.g., optimal) kernel may be identified. The neural network receives characteristics of the input matrices and determines relevancy scores for a list of possible kernels. Based on an ordered listing of kernels by relevant score, a kernel is selected from the list and utilized to perform the computation and provide the result.Type: GrantFiled: December 20, 2019Date of Patent: April 11, 2023Assignee: Nvidia CorporationInventors: Jonathan Edward Barker, Christopher Thomas Cheng, Paul Martin Springer, Wojciech Jablonski
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Patent number: 11625245Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.Type: GrantFiled: September 28, 2018Date of Patent: April 11, 2023Assignee: Intel CorporationInventors: Eriko Nurvitadhi, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu
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Patent number: 11614942Abstract: Devices and techniques for short-thread rescheduling in a processor are described herein. When an instruction for a thread completes, a result is produced. The condition that the same thread is scheduled in a next execution slot and that the next instruction of the thread will use the result can be detected. In response to this condition, the result can be provided directly to an execution unit for the next instruction.Type: GrantFiled: October 20, 2020Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Christopher Baronne, Dean E. Walker