Abstract: An integrated risk management tool includes a persistent object database to store information about actors (individuals and/or groups), physical surroundings, historical events and other information. The risk management tool also includes a decision support system that uses data objects from the database and advanced decision theory techniques, such as Bayesian Networks, to infer the relative risk of an undesirable event. As part of the relative risk calculation, the tool uses a simulation and gaming environment in which artificially intelligent actors interact with the environment to determine susceptibility to the undesired event. Preferred embodiments of the tool also include an open “plug-in” architecture that allows the tool to interface with existing consequence calculators. The tool also provides facilities for presenting data in a user-friendly manner as well as report generation facilities.
Abstract: Logic simulation includes storing a first state to identify in a simulation of a logic design whether a node included in the logic design has a logic high value Logic simulation also includes storing a second state to identify in simulation of the logic design whether the node has a logic low value and storing a third state to identify in simulation of the logic design whether the node has an undefined state. The logic simulation determines an output of the node in simulation of the logic design based on the first state, the second state, and the third state.
Type:
Grant
Filed:
August 29, 2001
Date of Patent:
October 31, 2006
Assignee:
Intel Corporation
Inventors:
William R. Wheeler, Timothy J. Fennell, Matthew J. Adiletta
Abstract: The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.
Abstract: A resource board for a circuit emulator holds programmable logic devices (PLDs) and other emulation resources such as random access memories (RAMs) and employs both hard-wired and network-based virtual signal paths to flexibly route signals between the emulation resources on the resource board and resources mounted on other resource boards, workstations and other external equipment. The resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.
Type:
Grant
Filed:
December 11, 2003
Date of Patent:
October 10, 2006
Assignee:
Fortelink, Inc.
Inventors:
Sweyyan Shei, Ming Yang Wang, Vincent Chiu, Neu Choo Ngui
Abstract: There are included the steps of receiving an operation input for defining a plurality of setting information pieces on a disk subsystem as a command by one operation, storing the defined setting information as a file, and sending the file to the disk subsystem.
Abstract: A system and method for intelligently generating computer code. The system being comprised of a local computer, which is connected to a remote computer via a network system or the Internet and which is capable of exchanging files with the remote computer. The local computer is further comprised of a document manager for transferring files between the local computer and the remote computer and for providing enhanced file management functions. The document manager works in connection with the server module, the site manager and the connectivity layer to connect to remote computers, to transparently exchange files with the remote computer and to manage server profiles and connection information that is related to remote computers and transferred files. Once the file is transferred to the local computer, the editor can modify the code associated with the file; the editor is also capable of creating new files.
Abstract: A wiring harness design is analyzed and module data is created automatically and stored for a plurality of harness modules representing wire and component element requirements for those modules, the modules being capable of assembly in selected combinations to create a complete harness.
Abstract: A tool for automatically generating a reduced size circuit model including inductive interaction properties is provided. Such inclusion of inductive properties in the reduced size circuit model allows for a more complete and accurate circuit model than those created by conventional methods. Further, a technique for automatically generating a reduced size circuit model including inductive properties that uses less memory space and operates faster than conventional methods is provided.
Abstract: Undesirable Steiner points in tetrahedralized meshes may be minimized by tetrahedralization processes that order element subdivision based on degree of freedom data for elements in the mesh and/or treat element degree of freedom as non-static during element subdivision. Applying look-ahead, breadth-first-search subdivision, and other strategic subdivision techniques further minimizes the need for Steiner points.
Type:
Grant
Filed:
August 30, 2001
Date of Patent:
August 29, 2006
Assignee:
International Business Machines Corporation
Inventors:
Stephen E. Fischer, Jeffrey B. Johnson, Ralph W. Young
Abstract: An optical route design system and method are described that can effectively calculate and display for a user how much margin there is in a design of an optical span. Basically, the optical route design system has a processor capable of determining whether a design of an optical span is an operable optical span and also capable of performing a margin analysis on the operable optical span to determine how much change the operable optical span can tolerate before the operable optical span becomes an inoperable optical span. The optical route design system also includes a display capable of presenting the results of the margin analysis to a user.
Abstract: To provide a method of assisting in the design of a vehicular suspension by allowing definition points inherent in suspensions to be easily recognized regardless of the different types and mechanisms thereof, and allowing specification values to be simply entered at the definition points. A method of assisting in the design of a vehicular suspension to generate a simulation model for a suspension using a CAD system includes the steps of indicating a suspension to be designed, opening a specification value entering window for entering specification values inherent in the indicated suspension, entering specification values at definition points inherent in the indicated suspension in the specification value entering window, and generating a simulation model based on the specification values at the definition points.
Abstract: A method and system for resolving testcase collection inconsistencies between a testcase list which includes testcases that have triggered harvest events within a simulation model, and a harvest hit table which records harvest events that have been triggered during simulation of the simulation model. First, the harvest hit table is updated from a simulation client to include a harvest event triggered by a testcase during simulation of the simulation model. The testcase is then collected within the testcase list. Finally, testcases identified within the testcase list are compared to testcases identified within the harvest hit table to determine inconsistencies therebetween.
Type:
Grant
Filed:
November 30, 2001
Date of Patent:
August 15, 2006
Assignee:
International Business Machines Corporation
Inventors:
Carol Ivash Gabele, Wolfgang Roesner, Derek Edward Williams
Abstract: The present invention is a Control System Architecture (CSA) for a multi-component armament system. The CSA provides dynamic reconfiguration of multiple nodes (e.g. a component, a subsystem, or a virtual simulation) in a Simulation-Emulation-Stimulation (SES) environment utilizing redundant client-server bus configuration of the nodes in a hierarchical model. The CSA provides for ease of configuration of nodes for any specific application, automated system reconfiguration capabilities to detect and bypass failed nodes or re-group available remaining nodes in the event of degraded mode operation, and expansion and/or downsizing of nodes without requiring a modification to the overall system architecture.
Type:
Grant
Filed:
December 18, 2000
Date of Patent:
August 15, 2006
Assignee:
BAE Systems Land & Armaments L.P.
Inventors:
Paul C. Huang, Omar A. Khan, Albert Sleder, Jr.
Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. Legacy instructions are translated into translated instructions. If the particular legacy instruction is an operand-setting instruction for storing a value of a precedent operand, a corresponding flag is set when the value of the precedent operand has not been determined. If the particular legacy instruction is an operand-using instruction for using the precedent operand, a check is made to determine if the corresponding flag is set.
Abstract: A system for automatic control of a process, comprising a process model using data and further comprising a data model for generating data for said process model and an empirical data extractor for extracting data from said process for said model, and wherein said data used by said process model is interchangeable between data obtained by said data model and data obtained by said extractor. The data model may be a partly statistical partly empirical orthogonal process model. The system is useful in allowing control systems using empirical prediction methods to perform automatic control before having built up a full results database.
Type:
Grant
Filed:
December 26, 2000
Date of Patent:
August 15, 2006
Assignee:
Insyst Ltd.
Inventors:
Arnold Goldman, Shlomo Sarel, Yehuda Hartman, Yossi Fisher
Abstract: A matrix reordering method performs reordering of elements of a coefficient matrix created based on coefficients of linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimination. Herein, degrees corresponding to numbers of non-zero elements are calculated with respect to all pivots included in the coefficient matrix. Then, a first pivot whose degree is under a threshold (mindeg+?) is selected from among the pivots of the coefficient matrix, while a second pivot whose critical path length is minimum is also selected from among the pivots of the coefficient matrix. Replacement of elements is performed between the first pivot and second pivot to complete reordering with respect to the first pivot. In addition, non-zero elements, which are newly produced by the Gaussian elimination of the first pivot, are added to the coefficient matrix.
Abstract: The present invention is directed to an advanced storage controller that is capable of providing parallel processing capabilities to a host processing system connected storage system to increase performance, functionality and reliability of the entire computing system. The advanced storage controller comprises at least one input interface and at least one output interface, a host device simulation component, a cache device component, a physical device component and a management component. Such an advanced storage controller further, includes one or more processor elements and storage elements, which may be shared by the components or dedicated to one component. Additionally, the advanced storage controller is scalable by the static or dynamic addition of components, processors and/or memory.
Abstract: A bus simulation apparatus for simulating a bus connecting a plurality of devices. Each of a plurality of simulated bus slot application interfaces prepares a receive task in response to a call from a simulated device corresponding to each of the plurality of the devices. The receive task obtains a communication handle for an application name of the simulated device. A communication handle management table relates the communication handle to the application name. A simulated bus manager, in response to a request for data transfer between the simulated devices along with the application name, sends data to the receive task of destination using the communication handle obtained by searching the communication handle management table based on the received application name.
Type:
Grant
Filed:
July 18, 2002
Date of Patent:
July 18, 2006
Assignee:
Matsushita Electric Industrial Co., Ltd.
Abstract: A method for maintaining updated antivirus files within a computer network comprising at least one user computer and at least one central service computer. Each of the user computer and central service computer has an antivirus database and the network is connected to an antivirus server. The method includes receiving a new antivirus file at one of the user computer and the central service computer and updating the computer's antivirus database. The antivirus databases of the central service computer and the user computer are compared to determine if one of the databases contain new antivirus files not contained within the other database. The central service computer and the user computer are each configured to send the new antivirus files to the other of the central service computer and the user computer to update the antivirus database.
Abstract: A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.
Type:
Grant
Filed:
March 25, 2002
Date of Patent:
July 11, 2006
Assignee:
Sun Microsystems, Inc.
Inventors:
Liang T. Chen, William kwei-cheung Lam, Thomas M. McWilliams