Abstract: A display device is capable of improving image quality including: a first and second substrate; a first and second color layer adjacent to each other between the first and second substrate, and arranged along a first direction; a third color layer including a first divided color layer adjacent to the first color layer in a second direction and a second divided color layer adjacent to the first divided color layer the first direction and adjacent to the second color layer in the second direction; a light blocking layer including a light blocking portion between the first and second color layer and a light blocking portion between the first and second divided color layer. The first, second and third color layer emit lights of different colors and at least two of them have different sizes. A width of the first and second light blocking portion is substantially equal.

Abstract: A wafer bonding method includes providing a first wafer including a first wafer surface, forming a first metal layer on the first wafer surface, and forming a first annular retaining wall structure including a first annular retaining wall and a second annular retaining wall surrounded by the first annular retaining wall. The first metal layer is formed between the first annular retaining wall and the second annular retaining wall. The method includes providing a second wafer including a second wafer surface, forming a second metal layer on the second wafer surface, and forming a second annular retaining wall structure including a third annular retaining wall and a fourth annular retaining wall surrounded by the third annular retaining wall. The second metal layer is formed between the third annular retaining wall and the fourth annular retaining wall. The method further includes bonding the first metal layer to the second metal layer.

Abstract: Ion sensor based on differential measurement comprising an ISFTET-REFET pair wherein the REFET is defined by a structure composed of an ISFET covered by a microreservoir where an internal reference solution is contained. The sensor comprises a first and a second ion-selective field effect transistor, an electrode, a substrate on the surface whereof are integrated the two transistors, connection tracks and the electrode and a structure adhered on the first ion-selective field effect transistor which creates a microreservoir on the gate of said first transistor, with the microreservoir having a microchannel which connects the microreservoir with the exterior and the microreservoir being filled with the reference solution.

Abstract: Light emitting diode (LED) devices, components and systems are provided. LED devices include a submount with a plurality of LEDs disposed thereon. The LEDs mounted on a submount can be spaced apart at predetermined dimensions to control the gaps between each of the plurality of LEDs. By controlling the gaps between LEDs the optical output from the LED device can be optimized, including improving emission and/or color uniformity, minimizing or eliminating deadspots in the light emission, and/or minimizing or eliminating an optical cross. A phosphor layer can be disposed on the plurality of LEDs and between the LEDs in the gaps therebetween.

Abstract: In accordance with another aspect, a power switch assembly includes a transistor package including a die case, a source bus tab extending from a first side of the die case, a drain bus tab extending from a second side of the die case, a first power bus rail operatively connected to the source bus tab of the transistor package and a second power bus rail operatively connected to the drain bus tab of the transistor package.

Abstract: LED packages are disclosed that are compact and efficiently emit light, and can comprise encapsulants with curved and planar surfaces. The packages can comprise a submount with a one or a plurality of LEDs, and in those with a plurality of LEDs each of the LEDs can emit the same or different wavelengths of light than the others. A blanket conversion material layer can be included on at least some of the LEDs and the submount. The encapsulant can be on the submount, over at least some of the LEDs, with each of the planar surfaces being vertical and aligned with one of the edges of the submount. The packages can also comprise reflective layers to minimize losses due to light absorption, which in turn can increase the overall package emission efficiency.

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die. A redistribution layer (RDL) structure is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active or passive element is disposed between the semiconductor die and the RDL structure. A molding compound surrounds the semiconductor die and the active or passive element.

Abstract: Methods of forming silicon nitride thin films on a substrate in a reaction space under high pressure are provided. The methods can include a plurality of plasma enhanced atomic layer deposition (PEALD) cycles, where at least one PEALD deposition cycle comprises contacting the substrate with a nitrogen plasma at a process pressure of 20 Torr to 500 Torr within the reaction space. In some embodiments the silicon precursor is a silyl halide, such as H2SiI2. In some embodiments the processes allow for the deposition of silicon nitride films having improved properties on three dimensional structures. For example, such silicon nitride films can have a ratio of wet etch rates on the top surfaces to the sidewall of about 1:1 in dilute HF.

Abstract: There are disclosed a semi-transmissive, semi-reflective display panel, a method of manufacturing the same and a display device. The semi-transmissive, semi-reflective display panel includes a display substrate having a transmissive region and a reflective region, and an optical device. The optical device includes a first reflective portion and a second reflective portion; the first reflective portion is configured to reflect the light irradiating the reflective region of the display substrate from a backlight source to the second reflective portion; and the second reflective portion is configured to transmit the light irradiating the transmissive region of the display substrate from the backlight source and reflect the light reflected from the first reflective portion to the transmissive region of the display substrate.

Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Abstract: Methods for fabricating a lateral voltage variable capacitor are disclosed. The voltage variable capacitor utilizes a dielectric material with an electric field dependent dielectric permittivity (dielectric constant). Various process steps are used including planarization to fabricate the lateral device structure.

Abstract: In one embodiment, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface, a first opening extending through a first material and through a portion of a second material located on the first material and a second opening extending from the bottom of the first opening to the top of a liner layer located on the upper surface of the floating gate conductor.

Abstract: A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.

Abstract: An integrated circuit (IC) package including a substrate comprising a dielectric, and at least one bridge die embedded in the first dielectric. The embedded bridge die comprises a plurality of through-vias extending from a first side to a second side and a first plurality of pads on the first side and a second plurality of pads on the second side. The first plurality of pads are interconnected to the second plurality of pads by the plurality of through-vias extending vertically through the bridge die. The second plurality of pads is coupled to a buried conductive layer in the substrate by solder joints or by an adhesive conductive film between the second plurality of pads of the bridge die and conductive structures in the buried conductive layer, and wherein the adhesive conductive film is over a second dielectric layer on the bridge die.

Abstract: System and methods for data logging are disclosed. The method comprising performing an initialization process, performing a data collection process in which data from a plurality of sensors is collected and time stamped, performing a time correction on the time-stamp data based on patterns of time and occupancy, performing an estimation of a light state based on the corrected time stamped data and determining an energy saving using an automatic light operation based on determined light state estimation.

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

Abstract: A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate.

Abstract: A semiconductor structure including one or more semiconductor devices on a wafer. The one or more devices having source/drain junctions. The semiconductor structure further includes a recessed middle-of-line (MOL) oxide layer, and an air-gap oxide layer including one or more introduced air-gaps. The air-gap oxide layer is positioned over the one or more semiconductor devices and the MOL oxide layer. A nitride layer is positioned over the one or more semiconductor devices. Trenches are formed through the nitride layer down to the source/drain junctions. A silicide fills the trenches.

Abstract: A semiconductor device is provided comprising a semiconductor substrate of a first conductivity type and a dummy trench portion having a main body portion and one or more branch portions, the main body portion formed in a front surface of the semiconductor substrate and extending in a predetermined extending direction, the branch portions extending from the main body portion in directions different from the extending direction. The semiconductor substrate has an emitter region of first conductivity type and a base region of a second conductivity type which are provided sequentially from the front surface side of the semiconductor substrate, and the dummy trench portion has a dummy trench which penetrates the emitter region and the base region from the front surface of the semiconductor substrate, and a dummy insulating portion which is provided within the dummy trench.

Abstract: A semiconductor device includes: an upper-surface electrode on an upper surface of a semiconductor element; a plated layer on an upper surface of the upper-surface electrode; gate runners penetrating the plated layer and formed to extend above the upper surface of the semiconductor element; and a metal connecting plate arranged above the plated layer and electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion at an end of the joint portion, the rising portion extending in a direction away from the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, a first distance, which is a shortest distance between the rising portion and the gate runner not intersecting the rising portion, is equal to or longer than 1 mm.