Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

Abstract: A method for manufacturing a semiconductor memory device includes forming a first silicon layer on a bottom conductive layer, transforming the first silicon layer into a first polysilicon layer, forming a second silicon layer stacked on the first polysilicon layer, and a third silicon layer stacked on the second silicon layer, transforming the second and third silicon layers into second and third polysilicon layers, wherein the first and third polysilicon layers have a first doping type, and the second polysilicon layer has a second doping type different from the first doping type, forming an amorphous silicon layer on the third polysilicon layer, and forming a top conductive layer on the amorphous silicon layer.

Abstract: A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.

Abstract: A method for fabricating self-aligned contacts includes forming a liner over a gate structure having a gate conductor and one sidewall spacer and etching an exposed gate conductor to form a recess extending less than a width of the gate conductor. A dielectric layer is conformally deposited to fill the recess between the liner and the one sidewall spacer to form a partial dielectric cap formed on the gate conductor. A self-aligned contact is formed adjacent to the one sidewall spacer of the gate structure that is electrically isolated from the gate conductor by the partial dielectric cap and the at least one sidewall spacer.

Abstract: Optoelectronic modules include a silicon substrate in which or on which there is an optoelectronic device. An optics assembly is disposed over the optoelectronic device, and a spacer separates the silicon substrate from the optics assembly. Methods of fabricating such modules also are described.

Abstract: According to one embodiment, a semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is provided between the separation portion and the first interconnection part, and has contact with the first interconnection part and the second semiconductor part. The p-type semiconductor region is provided between the separation portion and the second interconnection part, and has contact with the second interconnection part and the second semiconductor part.

Abstract: A semiconductor device includes: a semiconductor element; a heat sink including a first surface and a second surface, the semiconductor element being joined to the first surface, the second surface being a surface on an opposite side of the first surface; and a package that is in contact with the semiconductor element and the first surface of the heat sink, the package including a recess portion in an outer face, wherein the heat sink includes a thick portion, and a thin portion having a thickness that is smaller than that of the thick portion, and the thin portion is located on a line connecting an outer face of the semiconductor element and the recess portion in a shortest distance.

Abstract: A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.

Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer.

Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

Abstract: A method for manufacturing a semiconductor device includes forming a magnetic tunnel junction (MTJ) structure comprising a magnetic fixed layer, a non-magnetic barrier layer and a magnetic free layer, and forming a metal oxide cap layer on the MTJ structure, wherein forming the metal oxide cap layer comprises depositing a metal layer on the magnetic free layer, performing an oxidation of the deposited metal layer to form an oxidized metal layer, and depositing a metal oxide layer on the oxidized metal layer.

Abstract: A semiconductor structure formed based on selectively recessing a middle-of-line (MOL) oxide layer of the semiconductor structure including multiple gate stacks formed on a substrate. A cap layer of the multiple gate stacks is selectively recessed. An air-gap oxide layer introducing one or more air-gaps is deposited. Chemical-mechanical planarization (CMP) is performed on the deposited air-gap oxide layer.

Abstract: A present invention includes a negative electrode, a substrate, an adhesive layer, an insulation layer and a reflective layer sequentially stacked. A P-type semiconductor layer, a light emitting layer and an N-type semiconductor layer are sequentially stacked on the reflective layer to form an LED light emitting layer. A positive electrode, spaced from the LED light emitting layer, is further stacked on the reflective layer. The present invention further includes an electrical connection structure that penetrates through the insulation layer, and penetrates through, in a spaced manner from the insulation layer, the reflective layer, the P-type semiconductor layer and the light emitting layer. The electrical connection structure is electrically connected to the adhesive layer and the N-type semiconductor layer, and has a pattern distribution. The pattern distribution is least one strip-like shape to form the continuous electrode structure.

Abstract: A method for forming a floating gate memory cell includes: forming an active region on a semiconductor substrate; forming a gate stack on the active region, the gate stack including a first gate layer defining a floating gate of the memory cell structure, a dielectric layer formed on the first gate layer, and a second gate layer defining a control gate of the memory cell structure formed on the dielectric layer; forming first and second source/drain regions in the active region, self-aligned with the gate stack; forming an erase/injection gate on at least a portion of the dielectric layer and spaced laterally from the control gate, the erase/injection gate being proximate to and above the floating gate; and forming multiple contacts providing electrical connection with the first and second source/drain regions, the control gate and the erase/injection gate.

Abstract: A semiconductor device includes a diode provided with: a drift layer being a first conductivity type; a cathode region being provided in a back face side of the drift layer and being the first conductivity type; a second conductivity type region provided in a surface layer part of the drift layer; multiple trenches dividing the second conductivity type region into pieces by being provided deeper than the second conductivity type region, and configuring an anode region; a gate insulation film provided in a surface of the trench; a gate electrode provided in a surface of the gate insulation film; an upper electrode electrically connected with the anode region; and a lower electrode electrically connected with the cathode region. A width between the trenches is narrowest in the drift layer is defined as a mesa width. The mesa width is set to be equal to or greater than 0.3 ?m.

Abstract: To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.

Abstract: One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, and a gate structure adjoining opposing walls of the fin. The source contact extends along a vertical direction along the source region. The source contact includes a conductive material and is disposed in a trench in the semiconductor body, adjacent to the source region. The body region and the drain extension region are arranged one after another between the source region and the drain region.

Abstract: A method of fabricating polysilicon gate structure in an image sensor device includes depositing a gate dielectric layer on a surface of a substrate. Then a polysilicon layer is deposited over the gate dielectric layer. Next, a protection film is deposited over the polysilicon layer. A hard mask is formed over the protection film, and the polysilicon gate structure is patterned. Following that, the hard mask is stripped off. The protection film exhibits etching selectivity against the polysilicon layer and has a thickness of between 40 and 60 angstroms. The hard mask is removed by phosphoric acid solution wet etching process.

Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.

Abstract: A light emitting diode according to one embodiment comprises: a substrate; a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, which are on the substrate; a first pad electrode part on the first conductive semiconductor layer; a current blocking layer on the second conductive semiconductor layer; a second electrode on the first conductive semiconductor layer and the current blocking layer; and a second pad electrode part on the second electrode, wherein the width of the current blocking layer can become thicker as the current blocking layer becomes closer to the first pad electrode part from the second pad electrode part.