Patents Examined by G. Nagesh Rao
  • Patent number: 8101020
    Abstract: A crystal growth apparatus comprises a reaction vessel holding a melt mixture containing an alkali metal and a group III metal, a gas supplying apparatus supplying a nitrogen source gas to a vessel space exposed to the melt mixture inside the reaction vessel, a heating unit heating the melt mixture to a crystal growth temperature, and a support unit supporting a seed crystal of a group III nitride crystal inside the melt mixture.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: January 24, 2012
    Assignee: Ricoh Company, Ltd.
    Inventors: Seiji Sarayama, Hirokazu Iwata, Akihiro Fuse
  • Patent number: 8052794
    Abstract: A method for locally controlling the stoichiometry of an epitaxially deposited layer on a semiconductor substrate is provided. The method includes directing a first reactant gas and a doping gas across a top surface of a semiconductor substrate and directing a drive gas and a second reactant gas against the substrate separately from the first reactant gas in a manner that rotates the substrate while introducing the second reactant gas at an edge of the substrate to control each reactant separately, thereby compensating and controlling depletion effects and improving doping uniformity in resulting epitaxial layers on the substrate.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: November 8, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Joseph John Sumakeris, Michael James Paisley, Michael John O'Loughlin
  • Patent number: 8029620
    Abstract: In a first aspect, a method is provided for forming an epitaxial layer stack on a substrate. The method includes (1) selecting a target carbon concentration for the epitaxial layer stack; (2) forming a carbon-containing silicon layer on the substrate, the carbon-containing silicon layer having at least one of an initial carbon concentration, a thickness and a deposition time selected based on the selected target carbon concentration; and (3) forming a non-carbon-containing silicon layer on the carbon-containing silicon layer prior to etching. Numerous other aspects are provided.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: October 4, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Yihwan Kim, Zhiyuan Ye, Ali Zojaji
  • Patent number: 8025729
    Abstract: A device for heat treating (annealing) a III-V semiconductor wafer comprises at least one wafer support unit which is dimensioned such that a cover provided above the wafer surface is either spaced without any distance or with a distance of maximally about 2 mm to the wafer surface. A process for heat treating III-V semiconductor wafers having diameters larger than 100 mm and a dislocation density below 1×104 cm?2 is carried out in the device of the invention. SI GaAs wafers produced have an at least 25% increased characteristic fracture strength (Weibull distribution), an improved radial macroscopic and mesoscopic homogeneity and an improved quality of the mechano-chemically polished surface. The characteristic fracture strength is higher than 1900 MPa.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 27, 2011
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Manfred Jurisch, Stefan Eichler, Thomas Bünger, Berndt Weinert, Frank Börner
  • Patent number: 8016944
    Abstract: Methods and apparatus for producing nanoparticles, including single-crystal semiconductor nanoparticles, are provided. The methods include the step of generating a constricted radiofrequency plasma in the presence of a precursor gas containing precursor molecules to form nanoparticles. Single-crystal semiconductor nanoparticles, including photoluminescent silicon nanoparticles, having diameters of no more than 10 nm may be fabricated in accordance with the methods.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: September 13, 2011
    Assignee: Regents of the University of Minnesota
    Inventors: Uwe Kortshagen, Elijah J. Thimsen, Lorenzo Mangolini, Ameya Bapat, David Jurbergs
  • Patent number: 8016941
    Abstract: A method and apparatus for crystallizing a semiconductor that includes a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation, comprising amorphizing at least a portion of the second layer, applying a stress to the second layer and heating the second layer above a recrystallization temperature.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: September 13, 2011
    Assignees: Infineon Technologies AG, Samsung Electronics Co., Ltd.
    Inventors: Matthias Hierlemann, Ja-Hum Ku
  • Patent number: 7892354
    Abstract: A process for the detection of polymorphic or pseudopolymorphic forms of solid, molecular and crystallizing compounds, or of molecular, cocrystalline compounds or of solid solutions which consist of at least two solid, molecular and crystallizing compounds, in a series investigation using an apparatus for parallel investigations in vessels of an array under different conditions in each vessel, in which substantially only the amorphous form of the crystallizing compound, a solvate of the crystallizing compound or substantially only the amorphous form or a solvate of a compound in a mixture of at least two compounds is used as a suspension or solution, the solutions of amorphous compound having, at the same temperature, a higher content of crystallizable compounds than is achievable with a corresponding crystalline compound.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: February 22, 2011
    Assignee: Solvias AG
    Inventors: Fritz Blatter, Martin Szelagiewicz, Markus von Raumer
  • Patent number: 7887633
    Abstract: Techniques for the formation of silicon ingots and crystals using silicon feedstock of various grades are described. Common feature is adding a predetermined amount of germanium to the melt and performing a crystallization to incorporate germanium into the silicon lattice of respective crystalline silicon materials. Such incorporated germanium results in improvements of respective silicon material characteristics, mainly increased material strength. This leads to positive effects at applying such materials in solar cell manufacturing and at making modules from those solar cells. A silicon material with a germanium concentration in the range (50-200) ppmw demonstrates an increased material strength, where best practical ranges depend on the material quality generated.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: February 15, 2011
    Assignee: Calisolar, Inc.
    Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Anis Jouini, Dieter Linke, Martin Kaes, Jean Patrice Rakotoniaina, Kamel Ounadjela
  • Patent number: 7879147
    Abstract: Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm?2, and a dislocation density standard deviation ratio of less than 25%, and methods of forming same, are disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: February 1, 2011
    Assignee: Cree, Inc.
    Inventors: Xueping Xu, Robert P. Vaudo
  • Patent number: 7875115
    Abstract: This disclosure is aimed at providing a method for producing an epitaxial wafer allowing uniform occurrence of oxygen precipitate in a substrate plane in the radial direction in a base plate and excelling in the crystal quality of an epi-layer. A method for the production of an epitaxial wafer, characterized by using as a substrate a base plate of nitrogen- and carbon-added silicon single crystal having a nitrogen concentration of 5×1014 to 5×1015 atoms/cm3 and a carbon concentration of 1×1016 to 1×1018 atoms/cm3, having a crystal growth condition during the production of silicon single crystal in a range in which the whole surface of substrate becomes an OSF region, and being pulled at a cooling speed of not less than 4° C./minute between 1100 and 1000° C. during the growth of crystal, and depositing the silicon single crystal layer on the surface of the substrate by the epitaxial method.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: January 25, 2011
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Koji Fukuhara
  • Patent number: 7868708
    Abstract: The method of making uniform low-stress crystals includes immersing a seed crystal held at a temperature under its melting point in a melt in a crucible and drawing it from the melt. The crystal and/or melt are rotated relative to each other and a planar phase boundary surface is maintained between them by detecting a surface temperature of the melt and/or crystal and controlling temperature fluctuations by increasing or decreasing the rotation speed. The single crystals obtained by this method have a diameter ?50 mm and no visible growth strips in a fishtail pattern when a 2-mm thick sample is observed between crossed polarizers. These crystals have an index of refraction uniformity ?n of <1 ppm and a stress birefringence of <1 nm/cm at 193 nm, so that optical elements suitable for DUV lithography can be made from them.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: January 11, 2011
    Assignee: Schott AG
    Inventors: Gunther Wehrhan, Lutz Parthier, Daniel Rytz, Klaus Dupre, Lothar Ackermann
  • Patent number: 7863798
    Abstract: A nanoscale nanocrystal which may be used as a reciprocating motor is provided, comprising a substrate having an energy differential across it, e.g. an electrical connection to a voltage source at a proximal end; an atom reservoir on the substrate distal to the electrical connection; a nanoparticle ram on the substrate distal to the atom reservoir; a nanolever contacting the nanoparticle ram and having an electrical connection to a voltage source, whereby a voltage applied between the electrical connections on the substrate and the nanolever causes movement of atoms between the reservoir and the ram. Movement of the ram causes movement of the nanolever relative to the substrate. The substrate and nanolever preferably comprise multiwalled carbon nanotubes (MWNTs) and the atom reservoir and nanoparticle ram are preferably metal (e.g. indium) deposited as small particles on the MWNTs.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: January 4, 2011
    Assignee: The Regents of the University of California
    Inventors: Brian C. Regan, Alexander K. Zettl, Shaul Aloni
  • Patent number: 7857907
    Abstract: The present invention relates to a method for forming a layered structure with silicon nanocrystals. In one embodiment, the method comprises the steps of: (i) forming a first conductive layer on a substrate, (ii) forming a silicon-rich dielectric layer on the first conductive layer, and (iii) laser-annealing at least the silicon-rich dielectric layer to induce silicon-rich aggregation to form a plurality of silicon nanocrystals in the silicon-rich dielectric layer. The silicon-rich dielectric layer is one of a silicon-rich oxide film having a refractive index in the range of about 1.4 to 2.3, or a silicon-rich nitride film having a refractive index in the range of about 1.7 to 2.3. The layered structure with silicon nanocrystals in a silicon-rich dielectric layer is usable in a solar cell, a photodetector, a touch panel, a non-volatile memory device as storage node, and a liquid crystal display.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: December 28, 2010
    Assignee: AU Optronics Corporation
    Inventors: An-Thung Cho, Chih-Wei Chao, Chia-Tien Peng, Wan-Yi Liu, Ming-Wei Sun
  • Patent number: 7846252
    Abstract: A silicon wafer for an IGBT is produced by forming an ingot having an interstitial oxygen concentration [Oi] of not more than 7.0×1017 atoms/cm3 by the Czochralski method; doping phosphorus in the ingot by neutron beam irradiation to the ingot; slicing a wafer from the ingot; performing annealing of the wafer in an oxidizing atmosphere containing at least oxygen at a temperature satisfying a predetermined formula; and forming a polysilicon layer or a strained layer on one side of the wafer.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: December 7, 2010
    Assignee: Sumco Corporation
    Inventors: Shigeru Umeno, Yasuhiro Oura, Koji Kato
  • Patent number: 7842133
    Abstract: In a method of growing a single crystal by melting a raw material within a vessel under a nitrogenous and non-oxidizing atmosphere, the vessel is oscillated and the melted raw material is contacted with an agitation medium made of a solid unreactive with the melted raw material.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: November 30, 2010
    Assignees: NGK Insulators, Ltd., Osaka University, Toyoda Gosei Co., Ltd.
    Inventors: Makoto Iwai, Takanao Shimodaira, Shuhei Higashihara, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura, Shiro Yamasaki, Koji Hirata
  • Patent number: 7833345
    Abstract: A method for the treatment of a crystal, such as a lithium niobate crystal or lithium tantalate crystal, having nonlinear optical properties. The crystal comprises foreign atoms which bring about specific absorption of radiated light. The foreign atoms are transformed into a lower valent state by means of oxidation. Electrons, which are released during oxidation, are discharged from the crystal with the aid of an external power source.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: November 16, 2010
    Assignee: Deutsche Telekom AG
    Inventors: Karsten Buse, Matthias Falk, Konrad Peithmann
  • Patent number: 7833347
    Abstract: A nitride single crystal is produced using a growth solution containing an easily oxidizable material. A crucible for storing the growth solution, a pressure vessel for storing the crucible and charging an atmosphere containing at least nitrogen, and an oxygen absorber disposed inside the pressure vessel and outside the crucible are used to grow the nitride single crystal.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: November 16, 2010
    Assignees: NGK Insulators, Ltd., Osaka University
    Inventors: Makoto Iwai, Shuhei Higashihara, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
  • Patent number: 7833348
    Abstract: An object of the invention is to calibrate an upper pyrometer for indirectly measuring a substrate temperature at the time of epitaxial growth in a comparatively short time and with accuracy to thereby improve the quality of an epitaxial substrate. After calibrating an upper pyrometer by a thermocouple mounted to a temperature calibrating susceptor, a measured value of a lower pyrometer is adjusted to a calibrated value of the upper pyrometer. Then, a correlation line between substrate temperature indirectly measured by the upper pyrometer at the time of epitaxial growth onto a sample substrate and haze of a sample substrate measured immediately after epitaxial growth is set to indirectly measure a substrate temperature by the upper pyrometer at the time of epitaxial growth onto a mass-production substrate.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: November 16, 2010
    Assignee: Sumco Corporation
    Inventors: Naoyuki Wada, Hiroyuki Kishi
  • Patent number: 7833346
    Abstract: There is provided a group III nitride crystal growth method capable of obtaining a material which is a GaN substrate of low defect density capable of being used as a power semiconductor substrate and in which characteristics of n-type and p-type requested for formation of transistor or the like. A growth method of group III nitride crystals includes: forming a mixed melt containing at least group III element and a flux formed of at least one selected from the group consisting of-alkaline metal and alkaline earth metal, in a reaction vessel; and growing group III nitride crystals from the mixed melt and a substance containing at least nitrogen, wherein after immersing a plurality of seed crystal substrates placed in an upper part of the reaction vessel in which the mixed melt is formed, into the mixed melt to cause crystal growth, the plurality of seed crystal substrates are pulled up above the mixed melt.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: November 16, 2010
    Assignee: NGK Insulators, Ltd.
    Inventors: Minoru Imaeda, Yoshimasa Kondo, Ichiro Okazaki
  • Patent number: 7830027
    Abstract: The invention relates to inter-level realignment after a stage of epitaxy on a face (31) of a substrate (30), comprising the production of at least one initial guide mark (32) on the face of the substrate, this initial guide mark being designed so as to be transferred, during epitaxy, onto the surface of the epitaxied layer (36). The initial guide mark (32) is produced in such a way that, during epitaxy, its edges create growth defects that propagate as far as the surface of the epitaxied layer (36) to provide a transferred guide mark (37) on the surface of the epitaxied layer (36) reproducing the shape of the initial guide mark (32) and in alignment with the initial guide mark.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: November 9, 2010
    Assignees: Commissariat a l'Energie Atomique, Freescale Semiconductor, Inc.
    Inventors: Bernard Diem, Eugene Blanchet, Bishnu Gogoi