Patents Examined by G. Nagesh Rao
  • Patent number: 7829207
    Abstract: A manufacture method that can manufacture ZnO based compound semiconductor crystal of good quality. A ZnO substrate is prepared to have a principal surface made of a plurality of terraces of (0001) planes arranged stepwise along an m-axis direction, the envelop of the principal surface being inclined relative to the (0001) plane by about 2 degrees or less. ZnO based compound semiconductor crystal is grown on the principal surface.
    Type: Grant
    Filed: September 27, 2008
    Date of Patent: November 9, 2010
    Assignees: Stanley Electric Co., Ltd., Tokyo Denpa Co., Ltd., Tohoku University
    Inventors: Hiroyuki Kato, Michihiro Sano, Katsumi Maeda, Hiroshi Yoneyama, Takafumi Yao, Meoung Whan Cho
  • Patent number: 7829134
    Abstract: A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: November 9, 2010
    Assignee: Adesto Technology Corporation
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Patent number: 7824493
    Abstract: A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: November 2, 2010
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Toshiaki Ono, Wataru Sugimura, Masataka Hourai
  • Patent number: 7815733
    Abstract: A method of growing hexagonal boron nitride single crystal is provided. Hexagonal boron nitride single crystal is grown in calcium nitride flux by heating, or heating and then slowly cooling, boron nitride and a calcium series material in an atmosphere containing nitrogen. Bulk hexagonal boron nitride single crystal can thereby successfully be grown.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: October 19, 2010
    Assignees: NGK Insulators, Ltd.
    Inventors: Makoto Iwai, Katsuhiro Imai, Takatomo Sasaki, Fumio Kawamura, Minoru Kawahara, Hiroaki Isobe
  • Patent number: 7811383
    Abstract: The device for production of a monocrystalline or a multicrystalline material blank, especially a silicon multicrystalline blank, using the VGF method has a crucible with a rectangular or square cross section. A flat heating device, especially a jacket heater, which generates an inhomogeneous temperature profile, is arranged around the crucible. This temperature profile corresponds to the temperature gradient formed in the center of the crucible. The heat output of the flat heating device decreases from the top to the bottom end of the crucible. The flat heating device includes parallel heating webs, which extend in a meandering course. The heat outputs from the heating webs differ according to their different conductor cross sections. To avoid local overheating in corner areas of the crucible, constrictions of the cross sections of the heating webs are provided at inversion zones of their meandering course.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 12, 2010
    Assignee: Schott AG
    Inventors: Matthias Mueller, Markus Finkbeiner, Uwe Sahr, Ingo Schwirtlich, Michael Clauss
  • Patent number: 7799133
    Abstract: A crucible apparatus includes a hollow crucible body which is open at its upper and lower ends and a bottom plate which is formed separately from the crucible body and can close off the lower end of the crucible body. A space for receiving a molten material is formed by placing the crucible body atop the bottom plate. When molten material received in the space has solidified, the crucible body is raised off the bottom plate, and solidified material is pushed out of one end of the crucible body and removed from the crucible body.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: September 21, 2010
    Assignee: IIS Materials Corporation, Ltd.
    Inventors: Norichika Yamauchi, Takehiko Shimada
  • Patent number: 7794539
    Abstract: A method for producing Group-III-element nitride crystals by which an improved growth rate is obtained and large high-quality crystals can be grown in a short time, a producing apparatus used therein, and a semiconductor element obtained using the method and the apparatus are provided. The method is a method for producing Group-III-element nitride crystals that includes a crystal growth process of subjecting a material solution containing a Group III element, nitrogen, and at least one of alkali metal and alkaline-earth metal to pressurizing and heating under an atmosphere of a nitrogen-containing gas so that the nitrogen and the Group III element in the material solution react with each other to grow crystals.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: September 14, 2010
    Assignees: Panasonic Corporation
    Inventors: Hisashi Minemoto, Yasuo Kitaoka, Isao Kidoguchi, Yusuke Mori, Fumio Kawamura, Takatomo Sasaki, Yasuhito Takahashi
  • Patent number: 7794538
    Abstract: A suspension of particles is rapidly self-assembled with a minimal number of defects into a three-dimensional array of particles onto a substrate under simultaneous sedimentating and annealing forces. This array of particles may be ordered as an opal structure. Optionally, the synthesized structure may incorporate an electrolyte into the suspension and be used as a sacrificial form for micromoulding an inverse structure. The inverse structure may exhibit a photonic band gap. Optionally, necking and material composition may be adjusted after micromoulding. These structures are useful to a wide variety of applications. The photonic band gap structure may be heated to function as a light source. The light source may be fitted into standard sockets.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: September 14, 2010
    Inventor: Robert A Marshall
  • Patent number: 7794540
    Abstract: Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: September 14, 2010
    Assignee: NXP B.V.
    Inventors: Petrus Hubertus Cornelis Magnee, Johannes Josephus Theodorus Marinus Donkers, Xiaoping Shi
  • Patent number: 7790636
    Abstract: A method for configuring J electromagnetic radiation sources (J?2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1?S1|, |W2?S2, . . . , |WI?SI| is about minimized with respect to Pj=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 7785414
    Abstract: A process for manufacturing a wafer of a silicon carbide single crystal having: cutting a wafer from an ? (hexagonal)-silicon carbide single crystal so that the off-angle is totally in the range from 0.4 to 2° to a plane obtained in perpendicular to the [0001]c axis of the silicon carbide single crystal; disposing the wafer in a reaction vessel; feeding a silicon source gas and carbon source gas in the reaction vessel; and epitaxially growing the ? (hexagonal) silicon carbide single crystal on the wafer by allowing the silicon source gas and carbon source gas to react.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: August 31, 2010
    Assignee: Bridgestone Corporation
    Inventors: Takayuki Maruyama, Toshimi Chiba
  • Patent number: 7780783
    Abstract: The invention provides an apparatus for producing a single crystal, and a method for producing a silicon single crystal using the same. An apparatus for producing a single crystal includes a heating device which heats polycrystalline silicon raw material held in a crucible to form silicon melt, and a pulling up device which grows a silicon single crystal while pulling it up from the silicon melt accompanied with rotation. By providing the apparatus with a magnetic field generation unit which applies to the silicon melt a cusp magnetic field a shape of neutral plane of which is symmetric around the rotation axis of the silicon single crystal and is curved in the upward direction, various conditions for producing a silicon single crystal having a defect free region is relaxed, and a silicon single crystal having a defect free region is produced at high efficiency.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: August 24, 2010
    Assignee: Sumco Corporation
    Inventors: Norihito Fukatsu, Kazuyuki Egashira, Senrin Fu
  • Patent number: 7776152
    Abstract: Apparatus and method for growing and observing the growth of epitaxial layers on a wafer. The apparatus includes: epitaxial growth apparatus; a source of light mounted to illuminate an entire surface of the wafer in the apparatus during growth of the epitaxial layer on the entire surface of the wafer; and apparatus for observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The method includes growing the epitaxial layer on a surface of the wafer and observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The growing process is varied in accordance with the observation. With an epitaxial layer of gallium nitride (GaN) the entire surface of the wafer is observed for balls of gallium.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: August 17, 2010
    Assignee: Raytheon Company
    Inventors: William E. Hoke, Theodore D. Kennedy
  • Patent number: 7771532
    Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: August 10, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
  • Patent number: 7771531
    Abstract: Provided is a manufacturing method of a crystallized rare-earth thin films on a glass or a silicon substrate. This manufacturing method of a crystallized metal oxide thin film includes a step of retaining an metal organic thin film or a metal oxide film containing at least one type of rare-earth metal element selected from a group comprised of Y, Dy, Sm, Gd, Ho, Eu, Tm, Tb, Er, Ce, Pr, Yb, La, Nd and Lu formed on a substrate at a temperature of 250 to 600° C., and a step of crystallizing the organic metal thin film or the metal oxide film while irradiating ultraviolet radiation having a wavelength of 200 nm or less.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: August 10, 2010
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Tetsuo Tsuchiya, Tomohiko Nakajima, Akio Watanabe, Toshiya Kumagai
  • Patent number: 7772585
    Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: August 10, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
  • Patent number: 7754083
    Abstract: A solid hollow fiber cooling crystallizer and method for crystallizing aqueous and organic solutions are provided. The solid hollow fiber crystallizer (SHFC) for carrying out cooling crystallization of inorganic/organic microsolutes/macrosolutes from solution generally includes a bundle of non-porous hollow fibers mounted within a shell where a feed solution for crystallization flows through the lumen side of the hollow fibers and a cooling solution flows through the shell side to form nuclei and subsequently crystals in the feed solution at a temperature below its saturation temperature. The solid hollow fiber crystallizer may be combined with a mixing device, such as a completely stirred tank or static mixer, to further effectuate crystallization. The solid hollow fiber crystallizer may be operated in a number of modes including feed recycle mode, once through mode, SHFC-in-line static mixer in series mode, and SHFC-CST in series mode.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: July 13, 2010
    Assignee: New Jersey Institute of Technology
    Inventors: Kamalesh K. Sirkar, Dimitrios Zarkadas
  • Patent number: 7749865
    Abstract: A method for producing semiconductor wafers, from a semiconductor ingot, wherein an oxygen concentration distribution in the growth axis direction is measured in the ingot state (F2), a position at which the oxygen concentration is maximum or minimum in a range of a predetermined length is determined as a cut position according to the measurement results (F3), the ingot is cut in a perpendicular direction to the growth axis at the cut position into blocks each having the oxygen concentrations being maximum and minimum at both ends thereof (F4), each of the blocks is sliced, and thereby semiconductor wafers are produced. Thereby, there can be provided a technique by which when semiconductor wafers are produced from a semiconductor ingot, wafers having oxygen concentration being in a predetermined standard range can be certainly produced.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: July 6, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Makoto Iida
  • Patent number: 7749324
    Abstract: The present invention includes a method for casting a silicon ingot by using a continuous casting method by means of an electromagnetic induction, and a method for cutting the silicon ingot as a starting material into plural silicon blocks. When the silicon blocks with a square section are cut out, the sectional shape of the silicon ingot is set to be rectangular. Not less than 6 pieces of equal-sized silicon blocks are cut out from the silicon ingot, thereby enabling to enhance the manufacturing efficiency to a great extent. And since the amount of excision of the edge per silicon block is reduced, the production yield can be enhanced. Further, since the proportion of columnar crystals with large grain size inside the ingot can be increased, it becomes possible to enhance the conversion efficiency of a solar battery using the silicon block as a substrate material.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: July 6, 2010
    Assignee: Sumco Solar Corporation
    Inventors: Mitsuo Yoshihara, Kenichi Sasatani
  • Patent number: 7745854
    Abstract: It is to provide a substrate for growing a semiconductor, which is effective for suppressing an occurrence of surface defects different in type from hillock defects in case of epitaxially growing a compound semiconductor layer, particularly an Al-based compound semiconductor layer. In a substrate for growing a compound semiconductor, in which a crystal surface inclined at a predetermined off angle with respect to a (100) plane is a principal plane, an angle made by a direction of a vector obtained by projecting a normal vector of the principal plane on the (100) plane and one direction of a [0-11] direction, a [01-1] direction, a [011] direction and a [0-1-1] direction is set to be less than 35°, and the compound semiconductor layer is epitaxially grown on the substrate.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: June 29, 2010
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Hideki Kurita, Ryuichi Hirano