Abstract: In an electrochemical storage cell of the alkali metal and chalcogen type, the closure has at least two closure elements which are plate-shaped at least in some areas. A first closure element is fastened to the housing and a second closure element is fastened to the rod-shaped current collector. All closure elements are additionally connected on the same side to the insulating ring of the solid electrolyte and are insulated from each other.

Abstract: A process for making an integrated structure comprised of complementary MOS devices is described, where electrical isolation is provided by recessed field oxide regions and by field isolation implant regions. Starting with a single conductivity type semiconductor layer, such as P- type silicon, a first masking step is used to produce an N- type well therein. After this, a layer of silicon or silicide is formed through the same mask. In a second masking step, openings are made for the field isolation implant regions. The edge of the silicon or silicide layer determines the edge of the field isolation implant, which is therefore self-aligned to the edge of the well. This same mask is later used to determine the locations of the recessed oxide isolation regions. Subsequent masking steps are used to form polysilicon gate electrodes, source and drain regions of the active devices, contact holes and contact metal and interconnects.

Abstract: A method for forming a shallow and highly concentrated arsenic doped surface layer in a silicon bulk region includes the steps of forming an arsenic doped polysilicon layer in contact with a preselected area of a bulk region surface in which the surface layer is to be formed and completely oxidizing the polysilicon layer at a rate exceeding the rate at which arsenic diffuses in the bulk region. Since arsenic has a relatively high silicon/silicon dioxide segregation coefficient and the oxidation rate exceeds the arsenic diffusion rate, arsenic accumulates at the silicon dioxide/silicon interface during oxidation, and nearly all of the arsenic in the region of the polysilicon layer above the preselected area is driven into the bulk region surface by the oxidation to form an impurity layer having a very high surface concentration of arsenic.

Abstract: An overall method for manufacturing an IGFET device having extremely shallow source and drain regions and reduced gate to source and drain overlap capacitances is disclosed. For silicon MOS devices, the method also provides for the formation of metal silicide layers on polysilicon gate electrodes and interconnection paths and the source and drain regions in the same fabrication step. Source and drain regions are formed by oxidation of an arsenic doped polysilicon source layer formed to be in contact with areas in the silicon surface in which such regions are to be formed. The rate of oxidation of the source layer exceeds the rate at which arsenic diffuses in the silicon at the oxidation temperature. Owing to a high segregation coefficient of arsenic in silicon dioxide, nearly all of the arsenic in the source layer is driven into extremely shallow source and drain regions which acquire high surface concentrations.

Abstract: A method of fabricating semiconductor integrated circuit devices having a semiconductor region in a position separated by a predetermined distance from a dielectric isolating region provided on the surface of a semiconductor wafer, comprising the steps of forming a first mask to define the dielectric isolating region and semiconductor region, forming a second mask over the first mask so as to cover the region which is to become the semiconductor region, and removing the second mask after the dielectric isolating region has been formed by the first and second masks, to form the semiconductor region. The method thus permits the semiconductor region to be self-aligned with the dielectric isolating region.

Abstract: A method and apparatus is described wherein a buried double heterostructure laser device is formed utilizing epitaxial layers of quaternary III-V alloys of gallium indium arsenide phosphide and wherein the buried layer is formed by first etching the p-type top layer of the structure down to the quaternary active layer forming a mesa. A second etchant is then provided which preferentially etches the active layer. This etchant is used to undercut the top layer by removing the active layer on both sides of the top mesa surface providing a narrow strip of active layer underneath the undercut mesa. The undercut is then filled in by a heat treatment process which results in migration or transport of the binary top layer and binary bottom layer to fill in the undercut, leaving the active layer buried in the binary material. In an alternate embodiment of the invention, the two-step etching process plus the transport phenomena is utilized to form the mirror surface of a laser device.

Abstract: A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

Abstract: A method of controlling the partial pressure of at least one substance or substance mixture comprising arranging the substance or mixture of substances in a chamber, arranging at least one element containing the substance or mixture of substances in the chamber and selecting the structure or crystal structure of the element to provide the desired partial pressure in the chamber.

Abstract: Dopant atoms are diffused into a silicon wafer by heating the entirety of the silicon wafer with the dopant atoms to a predetermined diffusing temperature in a short period of time, and more specifically, by applying light onto the silicon wafer under such conditions that the temperature difference between a central part of the silicon wafer and its peripheral part is maintained within 65.degree. C. The above diffusion method permits to carry out diffusion of the dopant atoms into silicon wafers with high productivity but without inducing physical defects such as warping or slip lines. It requires a very short time period for effecting diffusion to a desired extent and it enables to make the depth of diffusion greater.

Abstract: Process for manufacturing insulated-gate semiconductor devices such as MOSFETs being with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. A two-stage polysilicon etch procedure is disclosed. The initial etch produces relatively narrow channels with substantially vertical sidewalls. Unetched portions of the polysilicon layer are used as masks during a first P type diffusion to form a shorting extension of the device base region and during the forming of a silicon nitride mask layer by a highly directional process, such as ion implantation, which avoids the formation of any nitride layer on the channel sidewalls. In a subsequent lateral etch step, previously unetched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures.

Abstract: A vertical insulated gate field effect transistor is made by providing a polycrystalline semiconductor layer on an insulating layer at a surface of an n-type semiconductor body, and thereafter forming gates of the IGFET by laterally diffusing a p-type impurity into the polycrystalline semiconductor layer below two opposite edges of a masking layer. A p-type zone and an n-type source zone are then formed at the surface of the semiconductor body by introducing the relevant impurities in the presence of the masking layer, and then by laterally diffusing these impurities below the gate with the p-type impurities for the p-type zone diffusing laterally farther beneath the gate than the n-type impurities of the source zone. The lateral extent of the source zone, the p-type zone, and the gates can all be predetermined in relation to the same edge of the masking layer which enables improved gate-channel alignment, and so minimizes Miller capacitance of the IGFET.

Abstract: A method of producing a bipolar type semiconductor device including the steps of: forming an insulating layer, consisting of an oxide film of the semiconductor substrate or a separate layer on a silicon semiconductor substrate or layer having a first conductivity type; forming a polycrystalline semiconductor layer on the insulating layer; forming a mask layer on the polycrystalline semiconductor layer; forming a first base region on the semiconductor substrate or layer by introducing an impurity of a second conductivity type, through the polycrystalline semiconductor layer; removing the polycrystalline semiconductor layer under the mask layer; forming an aperture on the insulating layer with the remaining polycrystalline semiconductor layer, or its oxide film, used as a mask; a second base region, which is placed in contact with the first base region, by introducing a second conductivity type impurity into the semiconductor substrate or layer through the aperture; and forming a first conductivity type emitter

Abstract: A method for producing a Group II-VI compound semiconductor crystal containing a Group VI element other than Te by a temperature-difference method for growing the crystal from a solution containing Te, the Group VI element and a Group II-VI compound crystal source where Te is used as a major component of a solvent and the crystal is grown at a relatively low temperature by maintaining the vapor pressure of the VI group element at a predetermined value. This method can form a practical p-n junction by using two solutions, one containing a p-type additive and the other an n-type additive, and contacting a substrate successively with each of the solutions for a predetermined time length.

Abstract: A method for producing an impurity containing semiconductor substrate includes depositing an impurity on selected portions of the substrate by placing a charge on the substrate and converting a gaseous impurity containing atmosphere into a plasma. The impurity may then be diffused into the substrate to a controlled and shallow depth by employing a laser or the like to selectively irradiate the impurity.

Abstract: A lateral selective area liquid phase epitaxy method useful for the fabrication of, for example, a double barrier buried heterostructure laser, is described.

Abstract: A high sheet resistivity, doped semiconductor resistor is made by a process which produces a resistor diffusion or ion implantation mask having a narrow dimension determined by a "sidewall" technique. The sidewall technique defines the narrow dimension by the thickness of a doped or undoped layer deposited on a different underlying layer having horizontal and vertical surfaces. The horizontal portion of the deposited layer is removed by anistropic etching to leave only the vertical portion. The vertical portion, if undoped, is removed to define a diffused or ion-implanted resistor. The vertical portion, if doped, optionally may be removed, after heating to form a diffused resistor, or may be left in place to form a resistor in shunt with the diffused resistor.

Abstract: A method for producing integrated MOS field effect transistors, particularly complementary MOS field effect transistor circuits (CMOS-FET's) is provided wherein a metal silicide level, comprised preferably of tantalum silicide, is utilized as an additional interconnect (11). In this manner, all contact areas (9, 10, 13, 14, 15) to active (MOS) regions (6, 7) and polysilicon regions (5) for the metal silicide level (11) and also for the metal interconnect (12) are opened before the precipitation of the metal silicides. The structuring of the metal silicide level (11) is executed in such a manner that the p.sup.+ regions of the circuit remain protected during a flow-spread of an intermediate oxide (17) comprised of phosphorous glass.

Abstract: A method of providing recessed oxide isolation layers employs prior art techniques to the point at which a photoetched recess has exposed the semiconductor surface in which the recessed oxide isolation layer is to be grown. The semiconductor wafer is then subjected to a nitride layer formation procedure. The nitride layer formed extends into a photoetched recess and forms a nitride layer on the side surfaces of the recess. The newly deposited nitride layer is subjected to an etching process which etches vertically only, exposing the semiconductor surface in a pattern defined by the nitride coated recess. Since the recess walls are lined with a nitride layer, subsequent oxidation growth is restricted to the recess defined by the nitride coated walls. There is no intrusion of the recessed oxide isolation layer into adjacent active areas of the semiconductor material. Thus, the full active width of adjacent areas of the semiconductor is preserved and greater utilization of the available surface area achieved.

Abstract: Disclosed here is an IGFET formed on the single crystal silicon substrate where the major plane surface is deviated within the range from 22 degree to 34 degree toward the crystallographic surface {1,1,1} from {1,0,0} or on the silicon epitaxial layer formed on said substrate. Here, generation of silicon nitride is suppressed, which is newly formed under the mask in the selective oxidation process using the silicon nitride as the mask and also is the main cause of lowering the breakdown voltage of the gate insulating film. In addition, various kinds of functional characteristics depending on the crystallographic surface orientation are not interfered at all. Thereby, the present invention can offer an IGFET which drastically improved the breakdown voltage failure rate of the gate insulating film while keeping the functional characteristics at the best condition.

Abstract: In a case where a semiconductor device is produced comprising at least one semiconductor element, an isolation region surrounding the semiconductor element and a thick silicon oxide layer lying on and around the semiconductor element, the thick oxide layer is formed by thermally-oxidizing the epitaxial layer having a buried layer and, at the same time, the isolation region is formed in the epitaxial layer by heating for thermal oxidation. Prior to a step of introducing impurities into the epitaxial layer, a patterned thin silicon oxide layer is formed. This thin silicon oxide layer is varied into the thick oxide layer by the thermal-oxidation treatment.