Abstract: An insulating film is prepared by oxidizing an amorphous silicon layer containing boron or boron and germanium. The amorphous silicon layer is partially oxidized inwardly from the surface of the amorphous silicon layer to form the insulating film, while the unoxidized portion of the amorphous silicon layer is used as a conductive layer. The amorphous silicon layer may contain boron or boron and an element of Group IV, for example germanium. The insulating film is utilized to fabricate a bipolar transistor.

Abstract: A method of fabricating a film of in-situ doped polycrystalline silicon having a surface that is free of microscopic hillocks includes the steps of providing a deposition chamber and a wafer therein on which the film is to be fabricated and introducing one gas containing silicon atoms and another gas containing dopant atoms into said chamber with respective flow rates; wherein the respective flow rates are gradually increased in an overdamped fashion over a start-up time interval of at least one minute from zero to respective steady state values while simultaneously the ratio of the respective flow rates is kept within 25% of the ratio of said steady state values.

Abstract: The high resistance of diffused electrical interconnection lines used for ground return paths in MOS field effect transistor (MOSFET) arrays limits their size and performance. Advantage is taken of the extra interconnection level available from conventional double-layer-polycrystalline silicon (polysilicon) processes to distribute ground potential to arrays, by means of a polycrystalline grid with direct contact to diffused electrodes therein, thus greatly reducing the deleterious effects of ground resistance. The proposed ground grid is integrated into the structure of a MOSFET ROM using a typical double polysilicon process. The first polysilicon level provides the conductive medium for said ground grid and the diffusing doping impurities that form contiguous source electrodes for the array MOSFETs. Gate electrodes thereof and word lines are formed out of the second polysilicon level. Drain electrodes are diffused and contacted by metallized output lines.

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word address lines and the bias lines for the capacitors are formed by metal strips. The gates of the access transistors and the capacitor gates are polysilicon. Metal-to-polysilicon contacts are made to connect the metal word lines to the polysilicon gates of the access transistors and to connect the metal bias lines to the capacitor gates.

Abstract: A method for producing a MISFET having a gate electrode formed at the base of a grooved recess. The grooved recess is formed with steep side-walls (e.g., be reactive ion etching, ion beam milling or by using an orientation dependent etchant) and gate and source and drain contacts are formed by the simultaneous deposition of conductive material (e.g., metal evaporated from a point source.) Steepness of the side-walls of the recess ensures separation of the conductive material, isolating the gate electrode from the remaining conductive material providing the source and drain contacts.A silicon MISFET may be produced, using a diazine catalyzed ethylenediamine-pyrocatechol-water solution etchant, and exposing the (110) crystal plane face of the silicon to the etchant to form the recess.

Abstract: An improved lift-off process for forming metallized interconnections between various regions on a semi-conductor device relies on the use of a particular polyimide in forming a protective mask over the device. The polyimide is a copolymer of an aromatic cycloaliphatic diamine and a dianhydride which allows the resulting structure to withstand particularly high temperatures in the fabrication process. In particular, the polyamide when subjected to high temperature metallization under vacuum remains sufficiently soluble to be substantially completely removed from the device by immersion in common organic solvents. This allows high temperature metallization as interconnects for integrated circuits.

Abstract: A method for producing a semiconductor element which can form a deep P-type impurity region by a diffusion of aluminum. A porous alumina layer is first formed on a semiconductor substrate. Then, a diffusion-protective layer formed of a material having a large oxygen-diffusion-inhibiting ability such as Al.sub.2 O.sub.3 is formed on the porous alumina layer. Subsequently, aluminum ions are implanted in the porous alumina layer through the diffusion-protective layer. Thereafter, a heat treatment is performed to diffuse the aluminum of the aluminum ion-implanted region in the semiconductor substrate, and a P-type impurity region is formed. Alternatively, a porous alumina layer is formed on the semiconductor substrate, and an aluminum layer is then formed thereon. The diffusion-protective layer is formed on the aluminum layer, and a heat treatment is then performed, thereby diffusing the aluminum forming the aluminum layer in the semiconductor substrate, and a P-type impurity region is thus formed.

Abstract: A solid tantalum electrolytic capacitor is formed by a method comprisinganodizing a tantalum sintered body for substantial dielectric film growth in a substantially aqueous electrolyte;anodically treating said anodized tantalum body in at least one fused salt selected from the group of nitrates of alkali metals, nitrates of alkaline earth metals and nitrites of alkali metals with an applied voltage which is as high as possible but within a range wherein capacitance-decrease of the anode formed in the aqueous electrolyte is not caused; andanodically treating said fused salt-treated tantalum body in a substantially aqueous electrolyte with an applied voltage which is as high as possible but within a range wherein re-anodization will not occur, the temperature of said fused salt being in the range of 250.degree. C. to 350.degree. C.

Abstract: A method of manufacturing an integrated circuit device including vertical static induction transistors (SIT) having a first recess between the gate region and the drain (or source) region to reduce the capacitance between both regions and a second recess on an outer surface of the SIT gate to reduce the gate capacitance and a minority carrier storage. The method includes the steps of removing a masking film on the SIT channel region while leaving the masking film at the portions of the gate region and the drain region; forming the first and the second recesses in the channel region; locally oxidizing the exposed channel region; and forming the gate region and the drain region by removing the masking film.

Abstract: An array of semiconductive photoconductor detectors is formed on a substr with which the array forms a heterojunction. The array has a whole or partial overlayer of the same material as the substrate. Ohmic connections are made on the detectors and conductive read-out leads are connected to these connections; the leads are made of a conductor that forms a Schottky barrier with the substrate and overlayer. Ohmic connections are made to the substrate and overlayer such that a voltage bias may be applied between the substrate-overlayer combination and the array. The bais is used to control the accumulation layer in the substrate beneath the array in order to maximize sesitivity.

Abstract: A method of forming a plurality of interconnected metal oxide semiconductor field effect transistors on P-type semiconductor substrate (10). A layer of oxide (14) is formed on the substrate (10) and then a polysilicon layer (16) is formed on top of the oxide layer (14). A layer of silicon nitride (18) is deposited on top of the polysilicon layer (16). The silicon nitride layer (18), polysilicon layer (16) and oxide layer (14) are selectively etched to form a conductor pattern. The conductor pattern defines a gate electrode and a plurality of interconnecting lines (42) that interconnect transistors to each other and to the peripheral circuits that drive the transistors. The source and drain regions (26 and 28) are ion implanted with arsenic ions. The exposed sidewalls of the polysilicon layer (16) are oxidized lateral and subjacent to the silicon nitride layer (18).

Abstract: Acid electroplating baths for bright zinc plating containing a zinc salt, ammonium chloride and bath additives which include a carrier component comprising an alkyl substituted ammonium propoxylate salt, preferably a trialkylammonium propoxylate salt, and a lower molecular weight alkyl substituted naphthalene sulfonic acid, or bath soluble salt thereof, in combination with other brighteners and grain refiners for providing bright, ductile, fine grained, adherent deposits over a broad current density range.

Abstract: A semiconductor device, such as a MOSFET or IGR, is fabricated with a base region having a deep portion for reducing parasitic currents. A wafer is provided having an N type layer on an appropriately doped substrate. A first oxide layer is formed on the wafer, and a refractory electrode layer is deposited on the first oxide layer. A first window is opened in the refractory electrode layer, and then silicon nitride is deposited on the wafer. A second window is opened in the silicon nitride layer, within the first window. A deep P.sup.+ base region is diffused into the wafer through the second window, and then a second oxide layer is selectively grown in the second window. The silicon nitride layer is selectively removed, thereby opening a third window, defined by the second window and the second oxide layer situated within the second window. A shallow P base region is diffused into the wafer through the third window, followed by diffusion of a shallow N.sup.+ region through the third window.

Abstract: An MOS-type VLSI device is made by a process which provides a planar surface yet maintains geometric control for narrow line widths. The field oxide is recessed by etching the surface of a semiconductor body using thick masking for active device areas. Deposition of field oxide with poor step coverage allows the sidewall to be removed, leaving the top of the field oxide at the same level as the original silicon surface. The thick mask areas are lifted off, resulting in a planar oxide-insulated pattern for formation of transistors or N+ conductive lines.

Abstract: A transistor and method of forming the same are disclosed. A thick mesa of dielectric material is grown on a semiconductor substrate and two or more layers of polycrystalline silicon grown on the vertical sides of the mesa serve a masking function to define the gate region of the transistor with high accuracy. The mesa and the two or more polycrystalline layers remain in the final device.

Abstract: A monolithic microwave integrated circuit including an integral array antenna. The system includes radiating elements, feed network, phasing network, active and/or passive semiconductor devices, digital logic interface circuits and a microcomputer controller simultaneously incorporated on a single substrate by means of a controlled fabrication process sequence.

Abstract: A method for element isolation utilizing insulating materials on a semiconductor substrate in which an oxidizable material layer of polycrystalline silicon or the like is formed overlying the substrate surface, the oxidizable material layer disposed at the element-isolation-forming regions is oxidized using an oxidation mask, the oxidation mask is removed and, if necesary at least part of the unoxidized oxidizable material below the mask is removed. Predetermined processes such as oxidation and diffusion are performed thereafter to form semiconductor elements such as MOS transistors and bipolar transistors with high packaging density and reliability.

Abstract: An apparatus is provided for registering a pattern on a mask plate with a pattern already formed on a semiconductor wafer. A reflector group is provided on the wafer comprising a plurality of reflectors having a predetermined shape, interval and alignment. Two window groups are provided at predetermined positions on the mask plate. Each window group comprises a plurality of windows having a predetermined shape, interval and alignment that corresponds to the shape, interval and alignment of the reflector group. One of the window groups is provided with a staggered phase relationship with the other window group such that when one of the wafer or the mask plate is moved relative to the other, variations in the quantity of light reflected by the reflector group and passed through the respective window groups is used to determine the relative position of the wafer and the mask plate.

Abstract: An improved process for the electrolytic production of aluminum by electrolysis of aluminum chloride in a molten salt electrolyte bath. The improved process is characterized by a reduction in solubility of the reduced aluminum metal as well as a smaller metal droplet size permitting closer anode-cathode spacing in the electrolysis cell and a lower electrical resistance. The improvement comprises performing the electrolysis in an electrolyte consisting essentially of from 0.5 to 15 wt. % aluminum chloride, from 0.5 to 40 wt. % of one or more alkaline earth metal chlorides selected from the class consisting of magnesium chloride, barium chloride, strontium chloride and calcium chloride, from 10 to 90 wt. % lithium chloride and the balance sodium chloride.

Abstract: Modulated signal levels in the range of 1 .mu.V, as is typical for radar returns, can be used to achieve a useful modulated optical signal that can be launched into a fiber optic waveguide for transmission to a remote location for signal processing. The device of the invention achieves such a conversion by suitably integrating a high gain bipolar transistor with an electroluminescent diode, such as a light emitting diode or diode laser, into a compact monolithic structure.In one structural configuration, the bipolar transistor comprises an emitter comprising a layer of doped n-(Al,Ga)As supported on a base comprising a layer of doped p-GaAs, in turn supported on a collector comprising a layer of undoped n-GaAs or n-(Al,Ga)As. The electroluminescent diode in this embodiment comprises a light-emitting diode formed by a p-n junction between the undoped n-GaAs or n-(Al,Ga)As layer and a supporting doped p-GaAs layer, in turn supported on a doped p.sup.+ -GaAs substrate.