Abstract: A bezel-free display comprises a display substrate and an array of pixels. Pixel rows and pixel columns are separated by row and column distances and connected by row and column lines, respectively. A column driver is electrically connected to each of the column lines and a row driver is electrically connected to each of the row lines. Row-connection lines are electrically connected to each of the row lines or row drivers. In certain embodiments, each pixel in the column of pixels closest to a display substrate edge is spatially separated from the edge by a distance less than or equal to the column distance. At least one row driver is spatially separated from the corresponding row by a distance less than the column or row distance, at least one column driver is spatially separated from the corresponding column by a distance less than the column or row distance, or both.

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

Abstract: An LED lighting device capable of discharging heat generated from a light emitting element to the outside the LED lighting device. An LED lighting device includes: a plurality of light emitting elements; a mounted substrate on which the light emitting elements are mounted; and an electrode portion configured to supply a current to the light emitting elements from outside the LED lighting device. On the mounted substrate, a wiring substrate is located. On the upper surface of the mounted substrate, the mounted substrate includes: a light emitting region in which the plurality of light emitting elements are mounted; an exposed region which is located on the outer side of the light emitting region and through which the upper surface of the mounted substrate is exposed; and a wiring region which is located on the outer side of the light emitting region and in which the wiring substrate is located.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes: a voltage conducting layer, at least part of which is in a display area; a voltage connecting terminal in a peripheral circuit area, and a conductive lead in the peripheral circuit area. The conductive lead includes: a first annular portion, a second annular portion, and a plurality of bridging portions. The first annular portion is connected to the voltage conducting layer, the second annular portion surrounds the first annular portion and connected to the voltage connecting terminal, and a first end and a second end of each bridging portion are connected to the first annular portion and the second annular portion respectively.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: transistor cells formed along a first surface at a front side of a semiconductor portion; a drain structure between the transistor cells and a second surface of the semiconductor portion opposite to the first surface, the drain structure forming first pn junctions with body regions of the transistor cells and including an emitter layer directly adjoining the second surface; and a metal drain electrode directly adjoining the emitter layer. An integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a charge type of the body regions is at most 1.5E13 cm?2. Further semiconductor device embodiments are described.

Abstract: A system and method for the fabrication of high efficiency OLED devices and more specifically, the fabrication of OLED panels optically coupled with impact resistant, transparent structures which permit operation of the OLED panel while providing impact resistance. The OLED device can be built directly on an impact resistant transparent structure, or attached to an impact resistant transparent structure after it is built on other types of substrate. The impact resistant transparent structure can be a toughened layer, such as a glass layer, an energy absorption layer, such as Polycarbonate (PC), or a combination of both. The OLED device is configured to transmit light through the impact resistant transparent structure to the viewer, and the impact resistant transparent structure provides impact resistance for the OLED from the force of any impacting object.

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.

Abstract: A display apparatus includes a flexible substrate, a thin-film transistor unit, and a light-emitting unit. The flexible substrate includes a display area has a first area, a peripheral area which is adjacent to the display area, and a first penetrating portion corresponding to the first area. The thin-film transistor unit is in the display area and at least a portion of the peripheral area. The thin-film transistor unit includes a thin-film transistor and an insulation layer and has a second penetrating portion at a location corresponding to the first penetrating portion. The light-emitting unit is on the thin-film transistor unit and includes a pixel electrode, an intermediate layer including an emission layer, and a counter electrode.

Abstract: The organic light emitting display panel includes a first electrode formed on a substrate, an organic light emitting layer formed on the first electrode, a second electrode formed on the organic light emitting layer, a front sealing layer formed on the second electrode, wherein the front sealing layer is formed by alternately laminating an inorganic barrier layer and an organic barrier layer at least once, and at least one capping layer formed between the lowest layer closest to the second electrode among a plurality of thin films of the front sealing layer and the second electrode and having a higher index of refraction than an index of refraction of the lowest layer.

Abstract: A p-channel tri-gate transistor has a silicon fin that protrudes from a bulk silicon substrate, a thin silicon-germanium active layer is formed on three sidewalls of the silicon fin, and a hole well is formed between the gate insulating film and the silicon fin in the active layer surrounded by the tri-gate by a valence band offset electric potential against the silicon fin for moving holes collected in the hole well along the active layer with a high hole-mobility. Thus, it is possible to have the effects of not only an ultra-high speed, low power operation, but also a body biasing through an integral structure of the silicon fin-body. The p-channel tri-gate transistor can be fabricated together with an n-channel FinFET transistor in one substrate by the same CMOS process.

Abstract: A display apparatus comprises a first substrate comprising a first external surface and a first internal surface; a second substrate having a second external surface and a second internal surface facing the first internal surface of the first substrate; and a display unit disposed between the first and second substrates and comprising an array of pixels. The first substrate comprises a first side connecting the first external surface and the first internal surface. In a cross section perpendicular to the first external surface, the first side comprises a first straight region and a first curved region located between the first straight region and the first internal surface. The second substrate comprises a second side connecting the second external surface and the second internal surface. The second side comprises a second straight region and a second curved region located between the second straight region and the second internal surface.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a device region defined by a trench in the substrate. The semiconductor device includes a plurality of fin-shaped active regions spaced apart from each other in the device region and extending in a first direction. The semiconductor device includes a protruding pattern extending along a bottom surface of the trench. Moreover, an interval between the protruding pattern and the plurality of fin-shaped active regions is greater than an interval between two adjacent ones of the plurality of fin-shaped active regions.

Abstract: The present technology relates to a solid-state imaging device, a method of manufacturing the same, and an electronic device capable of improving sensitivity in a certain wavelength band and at the same time reducing color mixture of light of other wavelength bands in a photoelectric conversion unit.

Abstract: A semiconductor device including a transistor having low leakage current between the drain and the gate is provided. The semiconductor device includes an insulating film provided so as to cover a corner of the first conductor and a second conductor provided so as to overlap with a corner of the first conductor with the insulating film provided therebetween. Variation in the thickness of the insulating film can be prevented by making the first conductor have a rounded corner. Furthermore, concentration of electric field due to the corner of the first conductor can be relaxed. Thus, the current leakage between the first conductor and the second conductor can be reduced.

Abstract: An organic light emitting display device has an optical multilayer film on an organic light emitting diode. The organic light emitting display device includes an organic light emitting element with a cathode, an anode, and an organic light emitting layer, and an optical multilayer film on the organic light emitting element. The optical multilayer film is constructed such that a full width at half maximum of light emitted from the organic light emitting element is larger than a full width at half maximum of light emitted from a structure in which the optical multilayer film is not used. The color shift depending on a viewing angle of the organic light emitting display device may be reduced to improve efficiency of the organic light emitting element.

Abstract: Provided is an organic light-emitting element for emitting white light in which an optical distance L1 between a first emission layer (52) and a reflective electrode (80) satisfies Expression (a), and an optical distance L2 between a second emission layer (72) and the reflective electrode (80) satisfies Expression (b): (?1/8)×(3?(2?1/?))<L1<(?1/8)×(5?(2?1/?))??(a); and (?2/8)×(?(2?2/?)?1)<L2<(?2/8)×(?(2?2/?)+1)??(b), and in which a refractive index of a first charge transport layer (51) formed between a light extraction electrode (4) and the first emission layer (52) at the wavelength ?1 is 1.70 or less.

Abstract: Disclosed are a backplane substrate that is capable of expressing high gradation even through a small pixel, a method of manufacturing the same, and an organic light-emitting display device using the same. Integration for ultra-high resolution is possible through structural modification.

Abstract: A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern.