Abstract: An organic EL display device includes a substrate and an organic EL element (electroluminescent element) provided on the substrate. The organic El display device includes a sealing layer that seals the organic EL element. The sealing layer includes silicon oxide films. Moreover, the degree of oxidation of the silicon oxide films is set to 1.2 or more and 1.8 or less.

Abstract: Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.

Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.

Abstract: A NOR-type three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a substrate, and laterally alternating sequences of respective active region pillars and respective memory stack structures. Each laterally alternating sequence is electrically isolated from the electrically conductive layers by a respective blocking dielectric layer at each level of the electrically conductive layers. Each memory stack structures include a memory film and a semiconductor channel material portion that vertically extend through the vertically alternating stack. The active region pillars include an alternating sequence of source pillar and drain pillars.

Abstract: The present disclosure discloses a thin film transistor array substrate including an active layer disposed on a base substrate, wherein the active layer includes a first active region and a second active region located in a same structural layer, the first active region has a material comprising poly-silicon, and includes a first channel region, and a first source region and a first drain region that are located at both sides of the first channel region, respectively, the first source region having a first contact layer disposed thereon, the first drain region having a second contact layer disposed thereon, and materials of both the first and second contact layers being boron-doped poly-silicon; and the second active region has a material comprising metal oxide semiconductor, and includes a second channel region and a second source region and a second drain region that are located at both sides of the second channel region, respectively.

Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.

Abstract: Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

Abstract: The present disclosure relates to a memory device having a hybrid insulating layer and a method for preparing the same. In detail, a memory device including a gate electrode on a substrate, a source electrode, and a drain electrode has a hybrid memory insulating layer between the gate electrode and the source and drain electrodes that is polarizable and includes a mixed material of vinyltriethoxysilane and organic matter to lead to hysteresis. According to the present disclosure, a memory insulating layer is formed as a hybrid insulating layer including a mixture of polyvinylphenol as the organic matter and vinyltriethoxysilane to complement the properties of an organic memory whereby increasing memory performance, and it stably operates at both low and high temperatures whereby having a wide usage range.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Abstract: The present invention relates to OLED devices and stacks for OLED devices that include a symmetric emissive-layer architecture. In one embodiment, the present invention relates to an emissive stack having three layers, wherein the top and bottom layers emit light in the same or similar color region while the middle layer emits light in a different color region than the other two layers. In such an embodiment, the three layers are in contact with each other with no other layers in between. The symmetric emissive-layer architecture of the present invention can be used to improve the color stability of OLED devices.

Abstract: A flexible organic light emitting display (OLED) device includes an organic emitting diode on a flexible substrate, an encapsulation film covering the organic emitting diode and including a first inorganic layer and an organic layer. The first inorganic layer is formed of a first material, and at least a portion of the first inorganic layer includes a dopant that increases the surface energy of the doped material compared to that of non-doped material.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

Abstract: There is provided a photoconductive semiconductor switch device comprising: a semiconductor substrate configured to generate electrons and holes using incident light thereto; at least one pair of conductive layers disposed on the semiconductor substrate, wherein one pair of the conductive layers consists of first and second conductive layers spaced apart from each other, wherein each of the first and second conductive layers contains abundant electrical carriers to have a low resistance; and first and second electrodes disposed on at least partially on the first and second conductive layers respectively. In this way, the application of the photoconductive semiconductor switch device may be widened.

Abstract: A lighting device and a method for producing a lighting device are disclosed. In an embodiment, the lighting device includes a carrier, at least one optoelectronic illuminant arranged on the carrier, the illuminant configured to emit light into an emission area and a color scattering layer located in the emission area, the color scattering layer configured to generate a color by scattering of light at a surface of the color scattering layer facing away from the illuminant.

Abstract: The low reflective display device a low reflective unit including a plurality of optical lens structures arranged in a position-corresponding manner to the plurality of sub-pixels thereon respectively; a light-reflective layer covering the side-wall face of each optical lens structure; and a light-absorbing member arranged to fill spaces between neighboring optical lens structures, wherein the bottom face of each of the plurality of optical lens structures completely covers the top face of the corresponding sub-pixel among the plurality of sub-pixels, wherein the bottom face of each of the plurality of optical lens structures receives all of light-beams generated from the corresponding sub-pixel, and wherein the bottom face of each of the plurality of optical lens structures has an area that is greater than or equal to a top face area of the corresponding sub-pixel.

Abstract: A method of fabricating a magneto-resistive random access memory (MRAM) cell with at least one magnetic tunnel junction (MTJ) is provided. The method includes disposing a metallic landing pad within a dielectric pad in a substrate and selectively depositing seed layer material over the substrate. This selective deposition forms a seed layer on which the MTJ is disposable on the metallic landing pad but not the dielectric pad.

Abstract: Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process.