Abstract: A serial-type analog-to-digital converter includes a plurality of serially connected folding circuits. Each folding circuit includes a first operational amplifier having an inverting input connected to an input terminal, and a second operational amplifier having a noninverting input connected to the input terminal. The bases of first and second transistors are respectively connected to the outputs of the first and second operational amplifiers. The emitters of the transistors are commonly connected to an output terminal. Feedback connections are provided for coupling the output terminal to the inverting input of each operational amplifier. Furthermore, circuitry is provided for calculating an estimated offset error based on maximum values of a folded analog signal provided at an output terminal of one of the folding circuits.

Abstract: A substantially constant current is divided between two lines in accordance with the relative values of an input voltage and a reference voltage respectively introduced to such lines. The currents through the first and second lines respectively charge first and second capacitances. The charges in the first and second capacitances respectively control the magnitudes of the currents flowing through first and second control members to charge the first and second capacitances. The control members are interconnected so that any difference between the flow of current through the control members and the associated capacitances between magnified. When the charge in an individual one of the capacitances reaches a particular value, a signal on an output terminal associated with the other capacitance changes from the first magnitude to a second magnitude. During this time, the signal associated with the first capacitance remains at substantially the first magnitude.

Abstract: A code converter includes a signal converter converting an input digital signal into an intermediate digital signal of two's complement. A subtracter has a minuend input node, receiving lower bits of the intermediate digital signal, and a subtrahend input node. A digital integrator receives an output from the subtracter, a digital comparator receives an output from the digital integrator, a delay unit receives an output from the digital comparator to execute a one-sampling period delay. An output from the delay unit is applied to the subtrahend input node of the subtracter, and an adder receives the remaining upper bits of the intermediate digital signal and the output from the digital comparator, a converted output digital signal being produced from the adder.

Abstract: An analog/digital converter operating on the principle of charge distribution includes a capacitor network having dual-weighted capacitors including two smallest capacitors. The capacitors each have two terminals. A comparator has a first input connected to one of the terminals of each of the capacitors and a second input and a reference switch is connected between each of the one terminals and a first reference potential. Other switches each selectively connect the other of the terminals of a respective one of the capacitors to an input analog potential, the first reference potential and a second reference potential. A coupling capacitor is connected upstream of the first input of the comparator.

Abstract: An encoder is rigidly mounted to a component shaft and allowed to float with it, saving the expense of a flexible coupling and improving accuracy. An easily assembled detent prevents rotation of the encoder housing with the shaft.

Abstract: A multiplying digital to analog converter using ladder networks and binary weighted load compensation to allow integration and video frequency operation. In one form, the circuit is configured from field effect transistors which incorporate by virtue of their structural and operational characteristics both the switching and resistive functions of R-2R ladder networks. The circuit is used to convert digital format words representing intensity and color (red, green and blue) into analog red, green and blue display drive signals. According to that configuration, the output of the digital to analog intensity word converter serves as the reference for the three digital to analog color word converters. Loading effects attributable to differences in the bit content of the color words are offset by a binary weighted switched load which is responsive to a digital compensation word. The switched load is also connected to the output of the intensity word converter.

Abstract: A semiconductor integrated circuit which is comprised of the following; a plurality of comparators which respectively compare analog values inputted for multiplication with individual reference voltages respectively, multiplication means which controls values outputted from those plural comparators by applying signals corresponding to digital values inputted for multiplication and outputs the product of the values outputted from those plural comparators and the digital values, and a complement operation circuit which converts the value outputted from multiplication means into complement when the digital value is negative.

Abstract: A system suitable for digitizing an analog audio signal, with the addition of analog dither to the audio signal and, after the digitization of the resulting analog audio/dither signal, the subtraction of digital dither from the digital audio/dither signal. For the production of the analog and digital dither signals, a digital dither generator is employed which generates digital dither of, e.g., 16 bits. The analog dither signal is derived from this 16 bits dither by first translating the same into analog dither of equivalent magnitude and then by reducing its magnitude to a value equivalent to e.g., 10 bits. The digital dither signal, on the other hand, is provided by reducing the magnitude of the 16 bits digital dither to that of substantially 10 bits. The analog dither signal is added to the audio signal, and the resulting analog audio/dither signal is translated by an analog to digital converter of, e.g., 16 bits into a digital audio/dither signal.

Abstract: A digital modulation signal is sampled by an A/D converter in a predetermined cycle. A phase interval P between a zero level crossing and the current sampling point using sampling data S.sub.i+1 at the current sampling point and sampling data S.sub.i at a sampling point which is located one point before the current sampling point. A phase P.sub.i+1 of the current sampling point is found using the phase interval P, a phase P.sub.i of the sampling point which is located one point before the current sampling point, a phase P.sub.i -1 of a sampling point which is located two points before the current sampling point and a phase P.sub.i-2 of a sampling point which is located three points before the current sampling point. A clock signal is detected using the phases P.sub.i+1 and P.sub.i. Digital data is detected using the phase interval P, the phase P.sub.i+1 and the sampling data S.sub.i at the sampling point which is located one point before the current sampling point.

Abstract: An unkown signal is sampled by simultaneously comparing its value with that of each of a plurality of predetermined monitoring levels. An independent time variable is recorded that represents the instant when the signal has a value equal to that of a given monitoring level. Equality of the signal value to that of a given level is detected regardless of whether the signal has increased or decreased to that value. The values of the monitoring levels are changed automatically whenever the signal has a value greater than the highest value monitoring level or less than the lowest value monitoring level. Signal sections having infinitely high rates of change over time may thus be accurately sampled and reconstructed.

Abstract: A multi-stage integrated decoder device has a special function which facilitates the simultaneous activation of a plurality and as many as all of its outputs. When it is used as a bit line decoder it is thus possible to activate a plurality and as many as all of the bit lines (including any redundant bit lines) of a block of storage cells of a semiconductor memory.

Abstract: An analog to digital converter system is disclosed as comprising a conversion circuit operative for developing a digital output corresponding to the magnitude of an input analog signal, a calibration port arranged for receiving digital calibration data from an external source, adjustable calibration circuitry associated with the conversion circuit, and an adjustment mechanism for adjusting the calibration circuitry in response to data applied to the calibration port.

Abstract: A process and data processing system are disclosed for compressing and expanding structurally associated multiple data sequences. The process is particular to data sets in which an analysis is made of the structure in order to identify a characteristic common to a predetermined number of successive data elements of a data sequence. In place of data elements, a code is used which is again decoded during expansion. The common characteristic is obtained by analyzing data elements which have the same order number in a number of data sequences. During expansion, the data elements obtained by decoding the code are ordered in data series on the basis of the order number of these data elements. The data processing system for performing the processes includes a storage matrix (26) and an index storage (28) having line addresses of the storage matrix (26) in an assorted line sequence.

Abstract: A digital-to-analog converter includes a sampled data sigma-delta modulator to resample and coarsely quantize the digital samples to be converted. The coarsely quantized samples are converted to sequences of pulses which are applied to a pulse sensitive analog integrator to develop analog representations of the digital signal.

Abstract: Input and reference voltages are respectively applied to the control elements of first and second transistors. This causes a substantially constant current to be divided between the first and second transistors in first time periods. In second time periods alternating with the first periods, the reference voltage is also applied to the control element of the first transistor to produce a current representation of the reference voltage. This causes the first and second transistors respectively to produce in the second periods voltages dependent only upon their relative characteristics. These voltages are introduced in the second periods to first and second capacitances to charge the capacitances when first switches such as transistors are closed. Subsequently in the second periods, the charges in the first and second capacitances are respectively transferred to third and fourth capacitances to charge the third and fourth capacitances.

Abstract: A method of and apparatus for converting between first and second digital data formats is disclosed whereby digital words of the first format are analyzed to detect an upper bandwidth limit of a corresponding analog signal in an interval thereof defined by such words and to determine the level of the analog signal at the beginning of such interval. A digital word of the second format is encoded with first and second pluralities of bits representing the determined upper bandwidth limit and the level of the corresponding analog signal at the beginning of the interval.

Abstract: A data outputting circuit including absolute value conversion circuit for converting digital data that is inputted with a determined sampling period into absolute value data, a register for storing the largest of the absolute value data provided within a predetermined period of time, a transferring register for receiving data and trransferring the data every predetermined period of time, and a compressing circuit adapted to compress compressing the data applied to the transferring register, whereby the circuit scale is reduced, and the data transferring time or the number of transferring lines is decreased.

Abstract: A coding method uses a pseudo-logarithmic compression law approximated by a straight line segment curve. Its code word on n+1 binary digits, where n is a positive invariant integer, has a lefthand part made up of a variable number p of binary digits having the same value (1) corresponding to the rank number of the segment concerned in the compression law and a righthand part, which may be absent, determining the interval within the segment concerned.

Abstract: The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S.sub.N) of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.N0 -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R.sub.D0 -R.sub.DN-1 and R.sub.DN0 -R.sub.DNN-1) compensates for transmission delays through the impedance elements that make up the strings.

Abstract: A parallel analog to digital converter and a method of processing at least two independnet signals therein are disclosed in accordance with the teachings of the present invention. The analog to digital converter has an improved sample and hold stage which, in addition to quantizing the analog signals, also multiplexes them. The sample and hold stage comprises at least two differential amplifier circuits, a latch stage, and a timing stage. Each differential amplifier circuit converts one analog input by comparing it to a reference voltage. The discrete output of the differential amplifier circuit is stored in the latch stage and outputted to an encoder. The timing circuit stage first selects one differential amplifier circuit to output its discrete signal, and then selects the latch stage to output its stored results. By sequencing through each differential amplifier circuit, the present invention effectively multiplexes the analog inputs.