Abstract: The invention provides a monolithic Y-bit resistive-ladder type digital-to-analog converter (DAC) having a unity gain inverting operational amplifier as an input buffer to the resistive ladder segment of the DAC. The reference voltage is applied to the input buffer amplifier. Optional bipolar operation is provided by applying a non-inverted reference voltage to the output of the resistive ladder segment of the DAC through a scaled resistance. Analog ground current cancellation is provided by a secondary X-bit R-2R ladder (where X Y) with the non-inverted reference voltage applied to it. The secondary bit ladder is switched in parallel with the top X bits of the main ladder, thereby supplying or sinking roughly the same amount of current as the X most significant bits of the main resistive ladder, but with opposite sense.

Abstract: A method for compressing and decompressing voice data enables efficient voice storage on small computers. Analog voice data is converted to digital voice data and the difference jumps between adjacent numbers in the digital voice data are measured. In the preferred embodiment, if the value of the jump is within the range +2 to -2, then a code value is assigned to that jump from zero to four where the code value equals the jump value plus two. If the jump value is outside the range, a jump is normally assigned a code value of five. Three adjacent codes are compressed to one code using the formula:Compression number=6.times.[6.times.(code 3)+ code 2] +code 1and at least this compression number is stored. If one or two of the code values in a group of three code values has a value of five, the actual jump value is stored after the compression number.

Abstract: A brushless DC motor useful as a driving source of a refrigerant compressor of a refrigerating apparatus or a fan. A position detecting means generates a control signal by detecting the terminal voltage on input-output terminals current to three-phase rotor drive coils. Filters convert the detected terminal voltages to smoothed signals. A mixing means generates three kinds of mixed signal from the smoothed signal and comparing means generates the control signal for switching a current path to the three-phase coils by a signal made by comparing the mixed signal with the smoothed signal. The current path to the coils is switched by a switching-driving part in turn on the basis of the control signal of the position detecting means.The present invention provides a brushless DC motor wherein current flowing to the drive coils can be switched without special position detecting elements.

Abstract: An automatic level control circuit for a multi-level quadrature amplitude-modulated (QAM) demodulator having a QAM detector, which produces baseband in-phase (P) and quadrature (Q) signals in response to an input QAM camer wave, and two analog-digital (A/D) convertors which convert the Q and P signals into two parallel digital signals. Automatic level control of the input level of the baseband signal to the A/D convertor is maintained constant by the combination of a reference signal generator in a feed back loop with each A/D convertor. The A/D convertor produces a decoded digital signal and the reference voltage generator, in response to those signals, provides reference voltage to the A/D convertor that are optimized in response to variations in input signal level.

Abstract: A variable gain analog to digital compression encoder apparatus and method is operational for `on the fly` gain adjustments without introducing significant distortion or noise in telephone conversation. An incoming analog signal is fixed gain reproduced as a first stabilized mid-operating point analog signal. A second stabilized mid-operating point analog signal is produced in inverse proportion to the first stabilized mid-operating point analog signal, in response to a signal tapped along a signal division of a difference between the first and second signals. The second signal is compression encoded at a predetermined rate to produce pulse code modulated signal samples. The tap may be varied to change the encoding gain, at any time, in accordance with operating requirements of a telephone apparatus.

Abstract: An analog-to-digital converter 10 employs a series of comparators 12, 14, 16 and 18. Each comparator includes at least one inverter consisting of a CMOS transistor pair including a P-channel transistor 22 and N-channel transistor 24. The threshold levels of the transistors 22, 24 are modified using focused ion beam implantation techniques to provide the comparators with monotonically increasing transistion levels.

Abstract: A semiconductor integrated circuit includes a plurality of comparators for comparing an analog input with reference voltage or voltages, holding means for holding a digital value, and control means for controlling the outputs of the plurality of comparators by a control signal responsive to the digital value to output the multiplication result of the output values of the plurality of comparators and the digital value. Thus, the integrated circuit can construct a circuit having functions of an A/D converter and a multiplier on one chip.

Abstract: Programmable transcoding device which sequences of binary words of variable lengths corresponding to strings of characters in a first alphabet are transcoded into other sequences of binary words intelligible in a second alphabet. The device is connected to digital systems exchanging sequences of words via interfaces provided with files. A CPU connected to the interfaces via a switching device receives the incoming sequences, and delivers transcoded outgoing sequences of binary words. An exchange management unit monitors the data transfers in the device and regulates the flows of words between the device and the digital systems. A terminal or microcomputer can also equip the device so as to produce transcoding tables to be downloaded in an RAM of the CPU.

Abstract: A high-resolution shaft encoder and a related encoding method for accurately measuring angular position and velocity of rotating shafts. The high-resolution shaft encoder includes an annular-shaped actuator ring that rotates at high speed, a shaft centered within the actuator ring, and an encoder housing. The shaft encoder generates measurements of shaft position .theta..sub.p and velocity .omega..sub.p, with respect to the encoder housing, from measurements of three time intervals t.sub.p, t.sub.r and .DELTA.t. These time interval measurements are computed from the output of a sensor element positioned on the shaft and a sensor element positioned on the encoder housing, both of which respond to an input actuation element positioned on the rotating actuator ring.

Abstract: An analog communication system includes a transmitter and at least one remote receiver for receiving an incoming signal carrying an analog component from a suitable transmitter. The transmitter and receiver are provided with circuitry for transmitting, receiving and recording and for playback of the analog componant of the transmitted signal at different rates. The system is adapted to transmit along messages at a high rate to conserve transmission time and to record and playback the message at a slower audible rate. The system circuitry includes a decoder which may be programmed to recognize an address code specific to a particular receiver or group of receivers or may be activated simply by the incoming signal without an address code, to emit the enable signal. The decoder includes rate memory for storing record and playback rates in memory sectors corresponding to the memory sector of RAM in which the message is stored.

Abstract: An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The A-to-D and D-to-A conversion rates are selected by the system control, responsive to data received from the signal processor.

Abstract: An analog to digital converter, adapted to convert an optical analog signal to an equivalent optical digital signal being one of x optically presented digital numbers defined by an n-bit digital word, where X=2.sup.n. The optical analog signal is light having an intensity variable over a range from a minimum to a maximum value. The analog to digital converter comprises a linear array of comparator means, a linear array of logic means, and a linear array of decoding means. The linear array of comparator means is responsive to the light at a plurality of input positions, x, and produces binary threshold signals which respresent a one-dimensional spacial reference having a length of corresponding to the magnitude of the sensed intensity. The linear array of logic means is responsive to the binary threshold signals and produces an optical index signal which is a one-point spacial reference having a location, an index postion, corresponding to the length of the one-dimensional spacial reference.

Abstract: There is provided a data processing apparatus for encoding or decoding binary data such as a magnetic disk or an optical disk in which a binary data sequence is converted to a binary code sequence which is suitable for a data processes. This data processing apparatus comprises: a code converter for converting the m-bit data in the binary data sequence to the n-bit code corresponding thereto; output means for outputting the n-bit code sequence corresponding to the binary data sequence; and DC-freeing means for restricting the DC component of the code sequence which is outputted from the output means. The code converter has a ROM table to store the data for code conversion and a register for converting the m-bit serial data to the parallel data and can be easily constituted by a programmable array logic.

Abstract: Each of data words has m bits. The m-bit data words are converted into corresponding n-bit code words. The n-bit code words are concatenated to form a bit sequence where the number of successive bits having a same binary value is limited to a range of a smaller value d to a larger value k. A code work W1 and also a following code word W2 are controlled to satisfy the limitation defined by the values d and k. The number of different code words forming an RLL code system is relatively large. For example, in respect of a first available RLL code word system, 8-bit data words are directly converted into 12-bit code words (Tw=0.667T) and the limitation defined by the values d and k equal to 2 and 10 respectively are satisfied. In respect of a second available RLL code word system, 6-bit data words are directly converted into 9-bit code words (Tw=0.667T) and the limitation defined by the values d and k equal to 2 and 23 respectively are satisfied.

Abstract: The invention centers around a system for interpolating between multiple pairs of main complementary signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is done with two strings (12) of a selected number of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.NO -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. The interpolated signals are taken from other pairs of corresponding nodes along the strings. The interpolation system is particularly suitable for use in an analog-to-digital converter of the folding type.

Abstract: A speed control device for d-c motors includes an IC control circuit having such a construction that a reference voltage is generated across two of its terminals C and D. Additionally, a current proportional to the armature current of the d-c motor is kept flowing in the terminal D at all times. A transistor is connected across the terminals C and D of the control circuit so that motor revolution can be changed linearly by means of a variable resistor connected in parallel across the base and collector of the transistor. With this arrangement, the revolution of d-c motors can be accurately controlled.

Abstract: A method and apparatus for generating signals representing a plurality (p) of n bit words corresponding to respective input signals. The apparatus comprises a basic word generator (7) for generating first signals representing m basic words (A-D) whereby the p words are the same as or are cyclic rearrangements of the n bits of the m basic words. Control means including combinatorial logic (33) determines the one of the p words corresponding to each input signal and generates corresponding control signals. Selection means including optical modulators (10-13, 20-25) are responsive to the control signals for selecting the appropriate first signal, if necessary after recycling by imposing selected delays, to constitute an output signal corresponding to the determined one of the p words.

Abstract: A comparator bank of an A/D converter comprising a plurality of comparators arranged into rows in a folded-back shape and a supply voltage line and a ground line in parallel with each other and connected to the comparators to provide reference potentials thereto according to a distribution shape which rises and falls continuously along the rows of the comparators whereby the linearity of the A/D converter is effectively maintained. The nodes of the comparators do not intersect and are arranged to successively become further from reference points set at the terminals of the supply voltage and ground lines.

Abstract: A method of and apparatus for converting between first and second digital data formats is disclosed whereby digital words of the first format are analyzed to detect an upper bandwidth limit of a corresponding analog signal in an interval thereof defined by such words and to determine the level of the analog signal at the beginning of such interval. A digital word of the second format is encoded with first and second pluralities of bits representing the determined upper bandwidth limit and the level of the corresponding analog signal at the beginning of the interval.