Patents Examined by Gene Auduong
  • Semiconductor memory device and method of operating the same
    Patent number: 9472291
    Abstract: A semiconductor memory device includes a memory string and a peripheral circuit. The memory string has a pipe cell, a plurality of memory cells, and at least one channel layer having a three-dimensional U-shaped structure. The peripheral circuit is configured to perform an erase operation on the pipe cell. A method of operating the semiconductor memory device includes selecting the memory string and performing the erase operation on the pipe cell.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 18, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jung Ho Park
  • Method of operating memory device using different read conditions
    Patent number: 9472275
    Abstract: A memory device and a method of operating the memory device are provided for performing a read-retry operation. The method of operating the memory device includes starting a read-retry mode, reading data of multiple cell regions using different read conditions, and setting a final read condition for the cell regions according to results of data determination operations on data read from the cell regions.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: October 18, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Kook Park, Young-Hoon Oh, Dae-Seok Byeon, Yong-Kyu Lee, Hyo-Jin Kwon
  • Semiconductor device and method of erasing the same
    Patent number: 9472290
    Abstract: A semiconductor device and a method of operating the same are provided. The method includes performing a multi-plane erase operation on selected planes; determining that the multi-plane erase operation has failed when a number of erase loops reaches a maximum number without successful completion of the multi-plane erase operation; determining whether there are passed planes amongst the selected planes; and performing a soft program operation on the passed planes.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: October 18, 2016
    Assignee: SK Hynix Inc.
    Inventor: Tai Kyu Kang
  • Transistors with source and word line voltage adjusting circuitry for controlling leakage currents and its method thereof
    Patent number: 9466342
    Abstract: According to one embodiment, a semiconductor memory device includes a source voltage adjustment circuit and a word line voltage adjustment circuit, which are configured to respectively supply a source voltage supply end and a word line switchingly with voltage-adjusted voltages, in response to a mode switching signal for switching between a retention state mode and an active state mode, wherein the source voltage supply end is connected to sources of MOS transistors forming a flip-flop of a memory cell, and the word line is connected to gates of access transistors.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: October 11, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinji Miyano
  • High temperature data retention in magnetoresistive random access memory
    Patent number: 9455015
    Abstract: Techniques and circuits for storing and retrieving data using spin-torque magnetic memory cells as anti-fuses are presented. Circuits are included to allow higher-magnitude voltages and currents to be applied to magnetic memory cells to intentionally break down the dielectric layer included the magnetic tunnel junction. Magnetic memory cells having a normal-resistance magnetic tunnel junction with an intact dielectric layer are used to store a first data state, and magnetic memory cells having a magnetic tunnel junction with a broken-down dielectric layer are used to store a second data state. Data can be stored in such a manner during wafer probe and then later read out directly or copied into other magnetic or non-magnetic memory on the device for use in operations after the device is included in a system.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 27, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Jon Slaughter, Jason Allen Janesky
  • Semiconductor device having CAL latency function
    Patent number: 9455019
    Abstract: One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: September 27, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Chikara Kondo
  • Semiconductor memory device
    Patent number: 9455024
    Abstract: A semiconductor memory device according to an embodiment includes first and second storages that enable writing and reading of data. The first decoding line and the third decoding line are electrically connected to each other. The first bit line and the third bit line are electrically connected to each other.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 27, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiaki Dozaka
  • Memory device including memory blocks and decoders to output memory block selection signals
    Patent number: 9449691
    Abstract: A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: September 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hosono, Tomonori Kurosawa
  • Temperature dependent voltage to unselected drain side select transistor during program of 3D NAND
    Patent number: 9443605
    Abstract: Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program disturb. The techniques may include compensating for how program disturb depends on the location of the word line that is selected for programming. In one aspect, the voltage that is applied to the control gates drain side select transistors of unselected NAND strings is adjusted during programming based on temperature. Greater temperature compensation may be applied when the selected word line is closer to the drain side select transistors.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 13, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Jian Chen, Yingda Dong, Jiahui Yuan
  • Semiconductor storage device
    Patent number: 9437283
    Abstract: The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply. The word line level fixing circuit includes multiple level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a fixed potential and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to turn-on of the second power supply.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: September 6, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Apparatus for boosting source-line voltage to reduce leakage in resistive memories
    Patent number: 9418761
    Abstract: Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Umut Arslan, Cyrille Dray
  • Rebalancing in twin cell memory schemes to enable multiple writes
    Patent number: 9418745
    Abstract: A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: August 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiang Chen, Toshiaki Kirihata, Derek H. Leu, Dan Moy
  • Anti-fuse type one-time programmable memory cell and anti-fuse type one-time programmable memory cell arrays
    Patent number: 9418754
    Abstract: An anti-fuse type OTP memory cell includes a first anti-fuse transistor having a first channel width, a first selection transistor sharing a first active region with the first anti-fuse transistor and having a second channel width that is greater than the first channel width, a second anti-fuse transistor sharing a program gate with the first anti-fuse transistor and having a third channel width, and a second selection transistor sharing a second active region with the second anti-fuse transistor and having a fourth channel width that is greater than the third channel width.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 16, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sung Kun Park
  • Resistive memory apparatus and reading method thereof
    Patent number: 9412445
    Abstract: A resistive memory apparatus and a reading method thereof are provided. In this method, two reading pulses are applied to a resistive memory cell, such that a first reading resistance and a second reading resistance of the resistive memory cell at different temperatures are sequentially obtained. Next, a resistive state of the second reading resistance is determined according to the reading resistances and the temperatures corresponding to the reading resistances. Thereafter, a logic level of storage data of the resistive memory cell is determined according to the resistive state of the second reading resistance.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: August 9, 2016
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Meng-Hung Lin, Ping-Kun Wang
  • Data storage device and operation method thereof
    Patent number: 9406386
    Abstract: A data storage device includes a nonvolatile memory having a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line. A memory controller divides first data to be programmed in the first memory cells into first and second data groups and divides second data to be programmed in the second memory cells into third and fourth data groups. The nonvolatile memory device performs a third program operation of the second data group and a fourth program operation of the fourth data group after sequentially performing a first program operation of the first data group and a second program operation of the third data group.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: August 2, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Duk Yu, Chul Bum Kim, Dongku Kang
  • Non-volatile dynamic random access memory (NVDRAM)
    Patent number: 9401198
    Abstract: A NVDRAM includes a first NV element coupled to a first terminal of a second NV element at a transfer node. A volatile cell has a transfer transistor coupled to the transfer node and has a storage node. A first NV line is coupled to the second terminal of the first NV element. Circuitry applies an alternated signal to the transfer node, couples the second terminal of the second non-volatile element to a second NV line, and applies a program signal across the first and second NV lines during a program mode that establishes a logic state. The circuitry applies a read signal across the first and second NV lines, couples the second terminal of the second NV element to the second NV line, and replaces the alternated signal with floating during a restore mode that loads the logic state into the storage node.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 26, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Anirban Roy
  • Memory device refreshing word line accessed in previous write operation
    Patent number: 9401193
    Abstract: A memory device includes a memory bank including a plurality of word lines, and a word line controller capable of activating a first word line, which is accessed during a previous write operation, among the plurality of word lines, while activating a second word line corresponding to an input address among the plurality of word lines, during an active operation.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 26, 2016
    Assignee: SK Hynix Inc.
    Inventor: Mun-Phil Park
  • Semiconductor memory device improving threshold voltage of unselected memory block and method of operating the same
    Patent number: 9396799
    Abstract: A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. The peripheral circuit may be configured to float a plurality of source select lines and a plurality of drain select lines of an unselected memory block of the plurality of memory blocks when the program operation is performed.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: July 19, 2016
    Assignee: Sk hynix Inc.
    Inventor: Keon Soo Shim
  • Conditional memory calibration cancellation
    Patent number: 9396778
    Abstract: A method and apparatus for conditional cancellation of a calibration procedure is performed. In one embodiment, a memory controller is coupled to memory. The memory controller is configured to convey data and a data strobe signal to the memory. The memory controller may conduct calibrations of a delay of the data strobe signal to ensure sufficient setup and hold time for the data. After an initial calibration, and at each of a number of periodic intervals, the memory controller may determine whether one or more parameters is within a specified range. If one of the one or more parameters is not within its respective specified range, another calibration of the data strobe delay may be performed. However, if each of the one or more parameters is within its respective specified range, the calibration may be canceled.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: July 19, 2016
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Kai Lun Hsiung, Rakesh L. Notani
  • Semiconductor memory device
    Patent number: 9390780
    Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: July 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyo-min Sohn