Patents Examined by Gene Auduong
  • Fully valid-gated read and write for low power array
    Patent number: 9384795
    Abstract: In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: David Paul Hoff, Jason Philip Martzloff, Robert Andrew Sweitzer
  • Semiconductor device and semiconductor system
    Patent number: 9384804
    Abstract: A semiconductor system is provided, which includes a controller configured to output an active command and test mode signals; and a semiconductor device configured to sense and amplify a pair of bit lines by generating a first power control signal of which a pulse width is adjusted in accordance with a combination of the test mode signals during an enable period of an enable signal generated by the active command, receiving a supply of a first power according to the first power control signal, and receiving a supply of a second power according to a second power control signal.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: July 5, 2016
    Assignee: SK HYNIX INC.
    Inventors: Sung Yub Lee, Geun Il Lee
  • Memory system and driving method thereof
    Patent number: 9378828
    Abstract: A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kuihan Ko, Yang-Lo Ahn, Kitae Park
  • Mismatch and noise insensitive sense amplifier circuit for STT MRAM
    Patent number: 9378795
    Abstract: A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel transistor is connected to a second p-channel transistor at the node B. A multiplexer is configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second re-channel transistor. The comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 28, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: John K. DeBrosse
  • Sense amplifier with pulsed control for pull-up transistors
    Patent number: 9373388
    Abstract: A sense amplifier is provided with a pair of first pull-up transistors that are configured to charge a corresponding pair of output terminals while a delayed sense enable signal is not asserted and to stop charging the corresponding pair of output terminals while the delayed sense enable signal is asserted.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: June 21, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Fahad Ahmed, Chulmin Jung, Sei Seung Yoon
  • Semiconductor memory device having a memory string that includes a transistor having a charge stored therein to indicate the memory string is defective
    Patent number: 9368211
    Abstract: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: June 14, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norichika Asaoka, Masanobu Shirakawa
  • Data independent periodic calibration using per-pin VREF correction technique for single-ended signaling
    Patent number: 9368164
    Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: June 14, 2016
    Assignee: Rambus Inc.
    Inventors: Pravin Kumar Venkatesan, Kashinath Prabhu, Makarand Shirasgaonkar, Wayne Dettloff
  • Memory system for processing data from memory device, and method of operating the same
    Patent number: 9368195
    Abstract: A memory system includes a memory device including memory blocks, each of the memory blocks including pages, each of the pages including memory cells that are electrically coupled to word lines, wherein the memory cells store data that is requested from a host; and a controller suitable for reading first data corresponding to a read command received from the host, from a page of a first memory block among the memory blocks, storing the first data in a buffer, providing the first data stored in the buffer, to the host, and writing and storing the first data stored in the buffer, in a page of a second memory block among the memory blocks.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jong-Min Lee
  • Apparatuses and methods for forming multiple decks of memory cells
    Patent number: 9362300
    Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 7, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
  • Multi-chip package and memory system
    Patent number: 9355685
    Abstract: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: May 31, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Matsunaga
  • Non-volatile semiconductor device
    Patent number: 9349464
    Abstract: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: May 24, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidehiro Shiga, Masanobu Shirakawa
  • Electronic device
    Patent number: 9349487
    Abstract: An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: May 24, 2016
    Assignee: SK hynix Inc.
    Inventor: Hoe-Gwon Jeong
  • Memory macro with a voltage keeper
    Patent number: 9343125
    Abstract: A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: May 17, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Derek C. Tao, Bing Wang, Allen Fan, Yukit Tang, Annie-Li-Keow Lum, Kuoyuan Hsu
  • Mismatch and noise insensitive sense amplifier circuit for STT MRAM
    Patent number: 9343131
    Abstract: A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel transistor is connected to a second p-channel transistor at the node B. A multiplexer is configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second n-channel transistor. The comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: May 17, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: John K. DeBrosse
  • Semiconductor apparatus capable of compensating for data output time and method for controlling the same
    Patent number: 9336840
    Abstract: A semiconductor apparatus may include a base die and a plurality of core dies stacked above the base die. Each of the core dies may be configured to output a strobe signal in response to a read command, and the base die may be configured to make remaining data output times correspond to any one data output time among respective data output times of the plurality of core dies, in response to the read command and the strobe signal.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: May 10, 2016
    Assignee: SK hynix Inc.
    Inventor: Sung Ho Kim
  • Non-volatile memory device having configurable page size
    Patent number: 9330765
    Abstract: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 3, 2016
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Three dimensional stacked nonvolatile semiconductor memory
    Patent number: 9330761
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: May 3, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Maejima
  • Non-volatile semiconductor memory device and memory system
    Patent number: 9330772
    Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 3, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yasushi Nagadomi
  • DRAM wordline control circuit, DRAM module and method of controlling DRAM wordline voltage
    Patent number: 9318186
    Abstract: A DRAM wordline voltage control circuit includes a sensing module, an oscillator and a charging pump. The sensing module is configured to receive a first control signal and a feedback signal corresponding to a wordline voltage signal, and generate a second control signal according to the first control signal and the feedback signal corresponding to the wordline voltage signal. The oscillator is electrically connected with the sensing module. The oscillator is configured to receive the second control signal and output an oscillating signal when the second control signal is enabled. The charging pump is electrically connected with the oscillator. The charging pump is configured to increase a voltage value of the wordline voltage signal when the oscillator outputs the oscillating signal.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: April 19, 2016
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Jen Chen
  • Lithography-friendly local read circuit for NAND flash memory devices and manufacturing method thereof
    Patent number: 9318499
    Abstract: A flash memory device comprising a local sensing circuitry is provided in a hierarchical structure with local and global bit lines. The local sensing circuitry comprise read and pass circuits configured to sense and amplify read currents during read operations, wherein the amplified read signals may be passed to a global circuit via the local and global bit lines.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: April 19, 2016
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie