Abstract: A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge.

Abstract: In a conventional analog buffer circuit composed of polycrystalline semiconductor TFTs, a variation in the output is large. Thus, a measure such as to provide a correction circuit has been taken. However, there has been such a problem that a circuit and driver operation are complicated. Therefore, a gate length and a gate width of a TFT composing an analog buffer circuit is set to be larger. Also, a multi-gate structure is adopted thereto. In addition, the arrangement of channel regions is devised. Thus, the analog buffer circuit having a small variation is obtained without using a correction circuit, and a semiconductor device having a small variation can be provided.

Abstract: In a lateral DMOS device 10 breakdown voltage is controlled by a voltage divider 50 coupled at opposite ends to the source 18 and drain 19. The divider node N1 between first and second resistive elements R1, R2 is connected to a second level conductive shield M2. ILD layer 34 isolates the shield M2 from first level conductive M1 contacts.

Abstract: A small size electronic component has a small direct current resistance value of conductor pattern and minimal dimensional irregularity of a conductor pattern. In order to form such a component, a photosensitive conductive paste applied on a ceramic substrate and is then exposed through a photo mask and developed so as to form a lower conductor pattern layer of a coil conductor pattern. Then an insulating paste is applied on the ceramic substrate so as to cover the lower conductor pattern layer and the insulating paste is removed with a solvent until at least the upper surface of the lower conductor pattern layer is exposed so as to form an inter-line insulating layer. Furthermore, after applying a photosensitive conductive paste as a film, the exposure and development operation is conducted again while using the photo mask so as to form an upper conductor pattern layer on the lower conductor pattern layer.

Abstract: A contact plug electrically connected with a MOS transistor is formed in a first interlayer dielectric. Then, a barrier metal material is deposited over the first interlayer dielectric and the contact plug, and patterned into a barrier metal electrically connected with the contact plug. After a SiN film is formed as an anti-oxygen-permeation film over the barrier metal and the first interlayer dielectric, the film is abraded by a chemical mechanical polishing technique until a top surface of the barrier metal is exposed. Then, a lower electrode material, a dielectric material and an upper electrode material are deposited in this order on the SiN film and the barrier metal, and then patterned such that a resulting lower electrode covers at least the entire upper surface of the barrier metal. Thereafter a second interlayer dielectric is deposited, and a heat treatment is performed in an oxygen ambient to recover film quality of a capacitor dielectric.

Abstract: A novel flash memory structure is disclosed, which includes a tunnel oxide layer on a semiconductor substrate, an array of gate electrode stacks formed on the tunnel oxide layer, and alternating source/drain regions formed between the stacks. A first dielectric layer is formed over the stacks and the substrate with a source line opening down to the source regions. A source line is formed above the source regions, partially filling the source line opening. The source line is located between the gate electrode stacks and has a surface level below a top surface of the stacks. A second dielectric layer is formed over the source line and the first dielectric layer with a plug opening down to the drain regions. A drain metal plug is formed over the drain regions, filling the plug opening. A metal bit line is formed over the second dielectric layer contacting the drain metal plug.

Abstract: Semiconductor islands are formed on an insulating substrate. A gate insulating layer is formed to traverse an intermediate region of each island, and a gate electrode with tapered sidewalls is formed thereon to leave wing-shaped gate insulating layer exposed at both sides. Ion implantation is done to form heavily doped regions in the semiconductor islands outside the gate insulating layers, and lightly doped drain regions under the wing regions of the gate insulating layer. An interlayer insulating layer is formed thereon to cover the gate electrodes, gate insulating layers, and the semiconductor islands. However, if the gate electrode layer and gate insulating film are patterned in the same shape, a step becomes high.

Abstract: An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates to form connected control gates. A second region is formed between adjacent, spaced apart, control gates.

Abstract: In a semiconductor device, a CoSi2 film is interposed between a pluglike contact and a barrier metal film as a silicide film. Consequently, excess reaction can be suppressed on a Ti/polysilicon interface between the pluglike contact or a pluglike local wire and the barrier metal film for stably lowering contact resistance.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: A guard ring structure formed around the periphery of a bipolar semiconductor device. A guard region (11) is formed in a substrate (1) of the device so as to extend adjacent a peripheral portion of the device. An insulating layer (3) is formed on the substrate between the peripheral portion of the device and the guard region (11). A polysilicon layer (13) is formed on the insulating layer (3) and covered with a layer of densified dielectic (14). Electrical interconnections are provided between the polysilicon layer (13) and the guard region (11) at spaced apart portions of the device where the guard structure does not need to be protected by the densified dielectric.

Abstract: A field effect transistor is made on a chip comprising a SiC-substrate. The transistor includes a plurality of densely stacked parallel transistor cells occupying totally a rectangular area. Each transistor cell has parallel strip-shaped regions forming the electrodes and active areas of the cell and each inner cell shares its drain and sources electrodes with neighbouring cells. In order to give a good power dissipation allowing an electrical high power of the transistor, the rectangular area has a very elongated shape and specifically it should have a width not larger than substantially 50 &mgr;m. In the rectangular area all the transistor cells have their strip-shaped regions located in parallel to short sides of the rectangular area and are generally very short considering the length of the rectangular area. Thus specifically also each cell has a length not larger than substantially 50 &mgr;m.

Abstract: A semiconductor memory device has a reference section which includes a first reference cell block and second reference cell blocks. The first reference cell block includes a second contact diffusion region which is arranged under a virtual ground line and is connected to this virtual ground line via a contact hole. The second reference cell blocks include first and third contact diffusion regions which are arranged under a bit line and can be connected to the bit line via contact holes as needed. Thereby, the number of reference cell blocks to be connected in series can be selected freely, allowing finer settings of a reference current value.

Abstract: A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a charge opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a charge opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a charge opposite that of the space charge of the second region.

Abstract: A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.

Abstract: On a SIMOX substrate having a plurality of STI layers and first conductivity type semiconductor layers disposed in the row direction, a stacked-layer structure SS is formed on a gate dielectric film formed on the first conductivity type semiconductor layer, the structure SS being made of a first polysilicon film, a second gate dielectric film and a second polysilicon film. Second conductivity type source and drain regions are formed in the first conductivity type semiconductor layer on both sides of the structure SS. In a plurality of source regions adjacent in the column direction between the stacked-layer structures SS, a common source line CSL is formed which is made of second conductivity type source region connecting semiconductor regions, source regions and conductive films formed on these semiconductor and source regions.

Abstract: In field-effect transistors, semiconductor clusters, which can extend from the source region to the drain region and which can be implemented in two ways, are embedded in one or a plurality of layers. In a first embodiment, the semiconductor material of the adjacent channel region can be strained by the clusters and the effective mass can thus be reduced by altering the energy band structure and the charge carrier mobility can be increased. In a second embodiment, the clusters themselves can be used as a canal region. These two embodiments can also appear in mixed forms. The invention can be applied to the Si material system with SiGe clusters or to the GaAs material system with InGaAs clusters or to other material systems.

Abstract: A surface treatment method for forming a fluorine-doped nitridized interface on a semiconductor substrate. The fluorine-doped nitridized interface may be formed using an ammonia plasma CVD process having a treatment gas doped with a fluorine component, such as carbon hexafluorine. The method may be employed as part of a LOCOS-based processing scheme in the manufacture of MOS semiconductor devices, such as DRAM devices.

Abstract: In a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and connected to the well, so as to fix a voltage at the well.