Abstract: An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. A field-shield (FS) isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes the edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of prescribed region is smaller than a channel length at the central portion.

Abstract: A memory cell comprised of three regions of a first-type deposited on a substrate of a second-type, a first insulating layer deposited over the substrate, a floating gate disposed over the first insulating layer, a second insulating layer disposed over the floating gate and the first insulating layer, a control gate disposed over the second insulating layer and partially extending over the floating gate, and a select gate disposed over the second insulating layer. The memory cell can be configured in four different ways. When placed in a memory array, a predefined number of memory cells can be grouped into blocks. By using a byte(block)-select transistor, the memory cells can be accessed and altered on block by block basis. The novel memory cells can be manufactured without requiring additional processing steps aside from those required in the manufacturing of the comparable flash memory cells.

Abstract: The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

Abstract: A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Abstract: In a semiconductor device which has capacitors respectively connected to multiple input terminals, and in which the remaining terminals of the capacitors are commonly connected to a sense amplifier, the capacitors and the sense amplifier are formed by utilizing a semiconductor layer on an insulating surface, whereby high-speed, high-precision processing of signals having a large number of bits supplied from the multiple input terminals is realized by a small circuit scale.

Abstract: There is described a semiconductor device whose structure is suitable for controlling the threshold values for operation of transistors, as well as for inexpensive fabrication of transistors whose threshold values for operation assume small values. A field-oxide film is formed on a silicon substrate through use of an oxidation-resistance mask, by means of the local oxidation of silicon (LOCOS) method. On the silicon substrate, there is formed an access transistor whose source/drain region is to be formed in active regions and whose channel region is to be formed in another active region. A protuberance is formed in the field-oxide film so as to bulge toward the active region where the channel region is to be formed. A bird's beak, which would grow during the course of formation of the field-oxide film, encounters difficulty in growing in the protuberance, as a result of which a trench is formed in a boundary area between the protuberance and the active region where the channel region is to be formed.

Abstract: A semiconductor device, that is, transistor, of a high withstand voltage having a LOCOS offset drain, which can cause complete depletion of a drift region and achieve both of an improvement in the junction breakdown voltage and a decrease in the on-resistance, and a method of producing the same. A semiconductor device comprising at least a p-type substrate, an n-type epitaxial layer formed on it, a p-well formed in the surface layer of the n-type epitaxial layer, an n-type source region formed in the surface layer of the p-well, an n-type drain region formed next to the drain region via an element isolation layer (LOCOS), and a gate electrode formed on the n-type source region and the element isolation layer, in which device a p-type buried layer containing an impurity in a higher concentration than that of the p-type substrate is formed, except just below the n-type drain region, in a surrounding pattern around the n-type drain region, and a method of producing the same.

Abstract: A technique for forming a high surface area electrode or storage node for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that a discontinuous layer is formed. A second conductive material layer is deposited over the discontinuous first conductive material layer, such that the second conductive material layer grows or accumulates on the discontinuous first conductive material layer at a faster rate than on the exposed areas of the substrate in the discontinuous first conductive material layer to form a rough conductive material layer.

Abstract: A thin film semiconductor device having improved operating characteristics and reliability of a thin film transistor formed on a glass substrate. The thin film semiconductor device has a thin film transistor 3 formed on a glass substrate 1 containing alkali metal. The surface of the glass substrate 1 is covered by a buffer layer 2. The thin film transistor 3 formed on this buffer layer 2 has a polycrystalline semiconductor thin film 4 as an active layer. The buffer layer 2 includes at least a silicon nitride film and protects the thin film transistor 3 from contamination by alkali metals such as Na and has a thickness such that it can shield the thin film transistor 3 from an electric field created by localized alkali metal ions (Na+).

Abstract: A method for fabricating an HVMOS transistor that can reduce snapback is disclosed. The semiconductor wafer comprises an N-type silicon substrate, and a P-type epitaxial layer formed on the surface of the silicon substrate. The HVMOS transistor comprises a first P-well region formed within the epitaxial layer, a second P-well region formed within the first P-well region a source region formed within the second P-well region, an N-drain region formed in the epitaxial layer, a gate, and an N-type diffused region formed both in the epitaxial layer and in the silicon substrate. The diffused region is under the first P-well region and overlaps the first P-well region.

Abstract: A reduced device geometry and increased device efficiency semiconductor memory device is provided. The method of manufacturing the semiconductor memory device includes forming shallow trench isolations (STIs) on the semiconductor substrate, forming a photoresist mask over the STIs, selectively etching the STIs to form curved surface area profiles, growing a layer of tunnel oxide (TOX) over exposed areas of the semiconductor substrate, forming a first polysilicon (poly) layer over the TOX layer and the STIs, chemical-mechanical polishing (CMP) the first poly layer, forming an oxide-nitride-oxide (ONO) layer over the first poly layer, and forming a second poly layer over the ONO layer.

Abstract: A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends out from the surface. A second substrate portion is disposed on the insulator region, and a second active region is disposed in the second substrate portion. Thus, by disposing a portion of the substrate on the isolation region, the usable substrate area is dramatically increased.

Abstract: Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.

Abstract: A nonvolatile memory cell of the type having a single lateral transistor includes source and drain regions separated by a channel region. A floating gate is provided over at least the channel region and is separated therefrom by a gate oxide, with a control gate over the floating gate and insulated therefrom. By having the floating gate extend over substantially its entire length at a substantially constant distance from the surface of the device, and providing the floating gate and the surface with similarly-contoured corners adjacent ends of the source and drain regions alongside the channel region, the nonvolatile memory cell can be programmed and erased using lower voltages than those required by priorart devices.

Abstract: In a SRAM, coupling between the adjacent bit lines is reduced and the limitation in reduction of the pattern area per memory cell is relaxed. The SRAM comprises SRAM memory cells arranged in a matrix and forming a cell array, pairs of bit lines BL and /BL extending in a column direction of the memory cell array, each of the pairs of bit lines being connected in common to the memory cells on the same column of the cell array, and the bit lines of each pair being arranged on both sides of the memory cells on the same column, a grounded line Vss, for supplying a ground potential to the memory cells, formed of the same layer as that of the pairs of bit lines and extending in the column direction, and a power supplying line Vdd, for supplying a power potential to the memory cells, formed of a layer different from that of the pairs of bit lines.

Abstract: A semiconductor device, in accordance with the present invention, includes a plurality of fuses disposed on a same level in a fuse bank. A plurality of conductive lines are routed through the fuse bank in between the fuses. A terminal via window is formed in a passivation layer over the plurality of conductive lines and over the plurality of fuses, the terminal via window being formed to expose the fuses in the fuse bank.

Abstract: An integrated capacitor is provided, incorporating a high dielectric constant material. In a disclosed method, a high k capacitor dielectric is formed in the shape of a container above a protective layer. After the dielectric is formed, inner and outer electrodes are formed, representing storage and reference electrodes of a memory cell. Contact is separately made through the protective layer from a storage electrode layer, which lines the inner surface of the dielectric, to an underlying polysilicon plug. The contact can be a thin layer lining the interior of the storage electrode layer, or can completely fill the container capacitor. In the latter instance, the contact can form part of the storage electrode and contribute to capacitance of the cell. Volatile dielectric materials can thus be formed prior to the electrodes, avoiding oxidation of the electrodes and underlying polysilicon plug, while also minimizing oxygen depletion through diffusion from the high dielectric constant material.

Abstract: Disclosed is a semiconductor device having low voltage characteristic and advantageous integrity simultaneously. The semiconductor device comprises a silicon-on-insulator (SOI) substrate of a stack structure comprising a base layer as a means for supporting, a buried oxide layer, and a semiconductor layer providing an active region; and a first transistor and a second transistor formed on the active region of the SOI substrate, wherein the first and second transistors are formed as a stack structure on one active region and they share one gate electrode, a drain region of the second transistor is electrically connected to the gate electrode and a source region of the second transistor is electrically connected to the active region.

Abstract: A fully amorphous thin film material that is related to ferroelectric compositions which is grown at low temperature, e.g., below 400° C., to yield a material with voltage independent capacitance, capacitance density of from about 1000 to about 10000 nF/cm2, leakage of <10−7 A/cm2, root mean square roughness <1 nanometer independent of film thickness, and an inverse capacitance that scales as a ratio of film thickness, reflecting uniform dielectric constant throughout the film. The film material may be employed for various capacitor structures, including decoupling capacitors, DRAM storage capacitors, feedthrough capacitors, bypass capacitors, capacitors for RC filters and capacitors for switched capacitor filters.

Abstract: The semiconductor device comprises a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.