Abstract: Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on an integrated circuit. A slave side arbitrator corresponding to a single slave component and coupled to multiple master components can be used to provide a master component access to a slave component.

Abstract: In one embodiment, a node comprises a first network interface and a second network interface. The node further comprises a first bus guardian that asserts a first bus guardian signal when the second network interface is allowed to transmit and a second bus guardian that asserts a second bus guardian signal when the first network interface is allowed to transmit. The first network interface is not allowed to transmit unless the second bus guardian asserts the second bus guardian signal. The second network interface is not allowed to transmit unless the first bus guardian asserts the first bus guardian signal.

Abstract: A semiconductor memory device includes first to third data buses, and first and second connection circuits. The first connection circuit inverts and transfers a first output signal on the first data bus read out from a memory onto the second data bus in response to a first selection signal, inverts and transfers a second output signal on the second data bus read out from the memory onto the first data bus in response to a second selection signal, and connects the first and second data buses in response to a reset signal. The second connection circuit inverts and transfers the inverted first output signal on the second data bus onto the third data bus in response to the first selection signal and transfers the second output signal on the second data bus onto the third data bus in response to the second selection signal.

Abstract: A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Abstract: Circuit having a bus, a first receiver circuit part coupled to the bus for processing a signal on the bus, a second receiver circuit part coupled to the bus for processing a signal on the bus, a transmitter circuit part coupled to the bus for outputting a signal on the bus, and a unit for preventing processing a signal on the bus by the first receiver circuit part in response to a control signal.

Abstract: A Multimedia (MMC)/Secure Digital (SD) form-factor compliant card apparatus can include a mode determining circuit connected to first and second pins of the card apparatus and configured to determine a type of host connected to the first and second pins based on comparing voltages at the first and second pins to an internal voltage level. Related adaptors and methods are also disclosed.

Abstract: A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

Abstract: A serial communication system includes an integrated circuit having a master serial interface; and a processor having a slave serial interface coupled to the master serial interface through a clock signal line and a data signal line. The slave serial interface is responsive to a read temperature command issued by the master serial interface to return a first temperature value associated with the processor.

Abstract: Described is a bus station (e.g., a sensor, an actuator, a gateway) which performs a primary device function and a secondary function (e.g., a bus monitor function). To perform the secondary function, the bus station is equipped with a bus monitor arrangement which allows the bus station to access, to detect and to further process telegram traffic carried on the bus system. Also described is a network equipped with a plurality of such bus stations and a method for carrying out such monitoring with the aid of the bus stations.

Abstract: A data communication system includes a master device, a plurality of slave devices, at least either a data transmission bus which connects the master device to a plurality of slave devices to transfer data from the master device to the slave devices in synchronism with a synchronous clock signal or a data reception bus over which the master device receives data from the slave devices in synchronism with a synchronous clock signal, and Chip Select signal lines which one-to-one connect the master device to the slave devices. The data communication system also includes communication drivers for setting a physical protocol of each slave device and a communication manager to arbitrate serial communications between the master device and the slave devices. The communication manager arbitrates serial communications to slave devices by their proper physical protocols. Communication protocols such as baud rates, clock polarities, and clock phases are switched by asserted Chip Select signal lines.

Abstract: A method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule are disclosed herein. A work item is removed from an enabled expansion bus schedule data structure and a coherency signal is then generated utilizing an expansion bus host controller. The work item is then reclaimed in response to the generation of the coherency signal. In one embodiment, the enabled expansion bus schedule data structure is a Universal Serial Bus (USB) asynchronous schedule including a plurality of queue heads.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A method and apparatus for fixed latency subtractive decoding. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: Disclosed are ways of providing a highly flexible high availability storage system. Disk drive carriers for insertion into enclosures in a storage system include several disk drives. The enclosures accept carriers that include drives of different sizes, and drives compatible with different storage technologies, for instance Fibre Channel, SATA, or SAS. Drives oriented in their carriers in a manner that allows them to be connected to a common medium via identical flex circuits that are configured based on the orientation of the drives. Redundant controllers include redundant serial buses for transferring management information to the carriers. The carriers include a controller for monitoring the multiple serial buses and producing storage technology specific management commands for the disk drives.

Abstract: An input/output module for implementing directions from a controller for sending and receiving signals to and from devices. The input/output module includes a microprocessor for communication with, and receiving programming from the controller. The input/output module further includes device communication connectors, each having number of pins, each pin for interconnection with a cable conductor to a device. The input/output module has an ASIC for each of the pins, providing a controlled interface with the corresponding pin. Each ASIC has interconnection apparatus, selectable by the microprocessor for providing a particular interface with the pin served by the ASIC.

Abstract: A technique according to the invention enables a single BIOS to support processors with or without 64-bit extensions efficiently. The BIOS creates a data structure having entries that correspond to elements stored in a state save area. The state save area elements themselves may be located at different addresses depending on whether or not the host processor includes 64-bit extensions. But the corresponding entries in the data structure are located at the same offsets within the data structure in either case. During execution of an SMI handler routine, the BIOS accesses the data structure whenever it needs to access elements of the state save area.

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Abstract: An electronic system comprises an initiator module and a target module addressable by the initiator module. The initiator module is activated by edges of an activation signal generated from a first clock signal having a frequency. A control module is activated by edges of a second clock signal having a frequency, which is at least twice as large as the frequency of the first clock signal. The control module is constructed so as, in response to an request for access to the target module, initiated by the initiator module on an active edge of the activation signal, to set a signal for blocking the activation signal before the next edge of the latter, and to reinitialize the blocking signal on the first active edge of the first clock signal which follows the indication by the target module that the processing of the request is terminated at the target module.

Abstract: Locks are placed in a convert queue in a way that compensates for queue bias. Rather than always placing a remote lock in a queue at the tail, a remote lock can be placed further up in the queue, and possibly be interleaved with local locks. As a result, remote processes are granted locks more frequently and swiftly. Locks are placed in a convert queue according based on queue placement factors, which are factors accounted for when placing a lock in a queue.

Abstract: In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is configured to initiate the virtual interrupt responsive to the interrupt state. In another embodiment, a method comprises storing an interrupt state describing a virtual interrupt in a storage area allocated to a guest. A processor initiates the virtual interrupt subsequent to initiating execution of the guest, responsive to the interrupt state. In still another embodiment, a computer accessible medium stores a plurality of instructions comprising instructions which, when executed on a processor in response to a physical interrupt: determine a guest into which a virtual interrupt corresponding to the physical interrupt is to be injected; and store an interrupt state describing the virtual interrupt in a storage area allocated to the guest.