Abstract: A system bus controller for a computer system and a related method are introduced. The computer system has at least a bus and a bus master electrically connected to the bus. The system bus controller includes a bus slave interface, a master queue, a bus master interface, a queue entries executor and a master queue management unit. Initially, any entry command transmitted over the bus by the bus master will be sequentially queued in a memory. Then, a corresponding acknowledge signal to release access of the bus is generated by the queue management unit. Then, the queued entry commands are sequentially executed to generate corresponding results, which will be caught by the bus master in an active or passive manner.

Abstract: An apparatus and method for connecting a plurality of computing devices, e.g. web servers, database servers, etc., to a plurality of storage devices, such as disks, disk arrays, tapes, etc., by using a stream-oriented (circuit oriented) switch that has high throughput, but that requires non-negligible time for reconfiguration is disclosed. An example of such stream-oriented switch is an optical switch. The preferred embodiment comprises a plurality of communication ports for connection to servers, and plurality of ports for connection to storage devices. The system decodes the requests from the computing devices and uses this information to create circuits, e.g. optical paths in embodiments where the stream-oriented switch is an optical switch, through the stream-oriented switch. The system uses these circuits to route traffic between the computing devices and the storage devices.

Abstract: An integrated semiconductor memory device for use within an integrated USB memory apparatus has a controller, a flash memory in communication with the controller, a USB interface circuit in communication with the memory controller, and an integrated circuit package for maintaining at least one of the controller, the flash memory, and the USB interface within the physical dimensions of a USB connector of the USB memory apparatus.

Abstract: An optical disc drive that includes a driving unit including a spindle motor to rotate an optical disc, an optical pickup to access the optical disc, and a connection board connected to a computer. A control board to control the driving unit, is installed at an interface device of the computer, separate from the driving unit, and is connected to the connection board.

Abstract: Systems, methodologies, media, and other embodiments associated with a system for producing a bus-type header-type field from a point-to-point data-type field are described. One exemplary system embodiment includes a logic configured to identify that a point-to-point transaction includes non-memory-data information encoded in a data flit, a logic configured to extract the non-memory-data information from the data flit, and a logic configured to produce a header-type field for a bus-type transaction produced by the virtual bus interface from the point-to-point transaction.

Abstract: The present invention relates generally to a logic arrangement, system and method which aid in a design of a fieldbus network configuration. In particular, the present invention includes certain functions for an automatic generation and verification of block and device tags, function block verification and modifications for function block type consistency based on information in the block profile, automatic allocation of function blocks into devices by an off-line scheduler, and a control strategy configuration system (which uses artificial intelligence to generate and maintain a fieldbus design knowledge-base). Accordingly, the user is able to easily configure the fieldbus network and devices residing thereon in an effective manner, as well as use the previously used configurations for establishing new fieldbus networks.

Abstract: A memory card integrating functions of the USB interface includes a memory chip inside a main body. A SD or MS control interface, a USB control interface, a controller, and a storage memory are built in the memory chip. Conductive bars are electrically connected to the memory chip and stick out from one end of the main body. An adaptor for the memory card includes an insertion socket to receive a SD memory card or a MS memory card. Conductive pins are positioned inside the insertion socket to be electrically connected to the memory card. A USB connecting head is provided at the front end of the insertion socket and electrically connected to the conductive pins inside the insertion socket. The SD memory card and the MS memory card can be inserted into the USB slot through the adaptor.

Abstract: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information interchange circuitry. The first signal select circuitry is configured to selectably provide a communication path between the information interchange circuitry and either the programmable logic circuitry or the first interface circuitry.

Abstract: To provide a method for controlling a transmission system with quick response in which plural electronic devices are connected to one host apparatus through a common data line. The method for controlling the transmission system of the present invention comprises: a step of transmitting a command signal for releasing the data line and suspending the processing through a command signal line to the electronic device occupying the data line in the state where one of the plural electronic devices is executing the processing that occupies the data line so as to make the electronic device release the data line and suspend the processing and to perform data transmission between the host apparatus and the other one of the electronic devices; and a step of resuming the suspended processing after the data transmission between the host apparatus and the other electronic device.

Abstract: A network device for handling data and a method for handling data in a network device are disclosed. The network device includes at least one media port and at least one high speed docking station, communicating with the at least one media port. At least one master is provided in the network device, where the at least one master is connected to the at least one high speed docking station. The master is configured to handle and process data received by the at least one media port and passed to the master through the at least one high speed docking station. The network device is configured to handle media ports of different media types. Thus, the device can handle data received through different media ports that have different media types with the same master, making the network device easily configured to meet a customer's needs.

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Abstract: An interrupt controller includes circuitry to process at least one end of interrupt (EOI) vector, the circuitry being capable of substantially simultaneously comparing the at least one EOI vector with a plurality of interrupts.

Abstract: A data processing system in accordance with an exemplary embodiment is provided. The data processing system includes a first host device operably coupled to a first PCI communication bus wherein the first host device substantially only performs tasks associated with facilitating communication through the first PCI communication bus. The data processing system further includes a first processing device operably coupled to the first PCI communication bus. Finally, the data processing system includes second and third devices both operably coupled to the first PCI communication bus. The second device is configured to request authorization from the first host device to transmit a first message through the first PCI communication bus, wherein the second device transmits the first message to the third device upon receipt of the authorization from the first host device even if the first processing device is not operable.

Abstract: A bus interface unit is adapted to receive transaction requests for at least two different targets. The bus interface unit monitors a capacity of a resource associated with servicing transaction requests to the targets, such as a posted write buffer. If a transaction request would fill the resource beyond a current remaining capacity of the resource such that the execution of other pipelined transactions would become stalled, the bus interface generates a retry response so that the request is retried at a later time, permitting other transactions to proceed while the resource drains.

Abstract: The invention is based on the idea that for a large data structure with N entries, memory space for the locks corresponding to the entries can be saved by performing a hashing function on a value that represents an entry into a hashed value 1 to M. This hashed value is used to index the table of M locks. The value of M is typically much smaller than the value of N thereby reducing memory space requirements. If M is chosen large enough and a good hashing function is selected, problems with collisions will be very small. Additionally, problems relating to deadlock occurring, when the hashed value of a second entry equals the hashed value of a first entry, are being addressed by swapping the hashed values of the first and second entries, when the hashed value of the second entry is smaller than the hashed value of the first entry.

Abstract: Systems and techniques to track deferred data transfers on a system-interconnect bus. A deferral response initiates storage of information corresponding to the response and tracking of progress for a requested data transfer. A master device, such as a bus adapter, may include a split-transaction repository, timers, and a split-transaction monitor. The master device may include both hardware and firmware components, and may be designed to handle split responses as defined by a Peripheral Component Interconnect Extended standard.

Abstract: A system includes logic configured for counting transitions between data on a bus and data to be put onto the bus. Where the counted transitions exceed a threshold, the data to be put onto the bus is complemented. As a result, complemented data is put on the bus where the threshold was exceeded and un-complemented data is put on the bus where the threshold was not exceeded.

Abstract: A computer system includes a primary display and a secondary display. The secondary display is coupled to a portable device. Information displayed on the secondary display includes information transmitted by the computer system via a short-range communication channel.

Abstract: The invention relates to a serial data transfer method for exchanging data between two electronic bus stations. The bus connection consists of two lines, the first line being dedicated to data/control signals and the second line being dedicated to a power supply voltage. Data transfer is started by pulling the first line to an activated potential for a first period of time, and then leaving the first line inactive for a second period of time. Data transmission commences via the first and second lines after the second period of time has elapsed. Preferably, data is transferred in a number of blocks in the data frame.

Abstract: A data transfer method for a Universal Serial Bus (USB) device is provided. The data transfer rate of a bulk transfer transmission in the USB is detected first for selecting a transfer transmission having a better data transfer rate between the bulk transfer transmission in the USB and an interrupt transfer transmission in the USB, so as to ensure the data transfer bandwidth in the USB is better utilized by the USB device.