Abstract: The sub-micron NMOS, PMOS and CMOS devices with methods for forming sub-micron contacts provide sub-micron devices and processes for manufacturing them with contacts down to 0.1 microns or less. All processes and devices utilize doped polysilicon as the electrodes for the device elements, and the preferred embodiment surrounds the polysilicon contacts with low temperature oxide covered by SOG which avoids all oxidation steps that could be detrimental in this contact size range. An optional alternative includes large contact area enlarging layers of silicide directly beneath each contact.

Abstract: First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60a , 60b) to control their conductance.

Abstract: A high degree of wafer-scale integration of normally incompatible IC devices is achieved by providing a plurality of segments (10), each segment having thereon one or more circuits, circuit elements, sensors and/or I/O connections (14'). Each segment is provided with at least one edge (12) having an abutting portion (12a) capable of abutting against a similar edge of a neighboring segment. The segments are placed on the surface of a flotation liquid (20) and are allowed to be pulled together so as to mate abutting edges of neighboring segments, thereby forming superchips (10'). Microbridges (22) are formed between neighboring segments, such as by solidifying the flotation liquid, and interconnections (26) are formed between neighboring segments.

Abstract: Disclosed herein is a bipolar transistor and a method of manufacturing the same. The present invention provides a bipolar transistor in which a collector layer, a base layer and an emitter layer are transversely arranged in sequence through a monocrystal silicon layer formed on an insulation layer of a semiconductor substrate and a method of manufacturing the same. According to the present invention, parasitic capacity between a base and a collector can be reduced and p-n junction capacity between the collector and the substrate can be removed, thereby to achieve high-speed operation.

Abstract: A silicon crystal evaluation method includes the step of measuring, at room temperature, an intensity of an oxygen impurity infrared absorption peak of each of a plurality of silicon crystals at a wavenumber of 1107.+-.3cm.sup.-1, Each of the silicon crystals contains oxygen impurities, the silicon crystals including an evaluated silicon crystal having an unknown thermal history and reference silicon crystals having respective known thermal histories. The second step is to measure, at a temperature equal to or lower than 10K, an intensity of an oxygen impurity infrared absorption peak of each of the silicon crystals at a predetermined wavenumber. A third step is to calculate a first peak intensity ratio between the intensity of the oxygen impurity infrared absorption peak of each of the silicon crystals at 1107.+-.cm.sup.-1 and the intensity of the oxygen impurity infrared absorption peak at the predetermined wavenumber.

Abstract: A diffusionless field effect transistor is formed at a face of a semiconductor layer (12) of a first conductivity type and includes a source conductor (36), a drain conductor (38) and a channel region (44). Source conductor (36) and drain conductor (38) are disposed to create inversion regions, of a second conductivity type opposite said first conductivity type, in the underlying source inversion region (40) and drain inversion region (42) of semiconductor layer (12) upon application of voltage. The transistor has a gate (54) insulatively overlying the channel region (44) to control the conductivity thereof.

Abstract: A Bi-MOS semiconductor device of a type having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate and a method of producing the same. The device includes a plurality of element isolation regions each thereof being composed of a first semiconductor region formed in the semiconductor substrate and having the same type of conductivity as the semiconductor substrate, and a thick insulation layer formed on the first semiconductor region, and at least one of an emitter electrode and a collector electrode formed in the bipolar device, gate electrodes formed in the MOS devices, a low-resistivity polycrystalline layer formed by a buried contact from one of the MOS devices and a high-resistivity portion formed by a high resistivity polycrystalline silicon layer connected to the low-resistivity polycrystalline silicon layer are formed from a polycrystalline silicon layer formed by the same layer formation.

Abstract: In a semiconductor device comprising a plurality of planar high-voltage insulated-gate field-effect transistors in which offset regions are provided in portions of the semiconductor substrate near the junctions of the adjacent drain regions and near the substrate surface, low impurity concentration offset regions are formed in the semiconductor substrate in such a manner that each low impurity concentration offset region is coupled the source region and is located between the drain regions of the field-effect transistors adjacent to each other and near the semiconductor surface, whereby reduction of the "on resistance" is achieved without affecting the FET sustaining voltage.

Abstract: An active device such as an HEMT is formed on a GaAs substrate, and characteristics of this active device formed are measured. A circuit pattern of a passive circuit device including a serial microstrip line is simulated on the basis of the results of this measurement, and a circuit pattern obtained by the simulation is directly drawn on a substrate to form the passive circuit device, thereby to fabricate an MMIC. Accordingly, the passive circuit device is formed in conformity with the characteristics of the active device for each chip.As a result, the variation in characteristics of the active device is canceled, to obtain an MMIC superior in matching.

Abstract: There is disclosed a method of manufacturing an integrated circuit, comprising: the first step of growing a first epitaxial crystal on a compound semiconductor substrate, removing an unnecessary region of the first epitaxial crystal to form a residual portion, and covering the residual portion with a selective growth mask, the second step of growing a second epitaxial crystal on an exposed substrate portion, removing an unnecessary portion of the second epitaxial crystal to form a residual portion of the second epitaxial crystal, and covering the residual portion of the second epitaxial crystal with a selective growth mask, and third step of growing a third epitaxial crystal on an exposed substrate portion and removing an unnecessary region of the third epitaxial crystal, wherein the first to third epitaxial crystal form any one of a pin photodiode crystal, a heterojunction bipolar transistor crystal, and a high electron mobility transistor crystal, and are different from each other.

Abstract: A semiconductor diode has three adjacent regions. The doped regions are doped in the same manner and are separated from one another by a third, intrinsic region. The intrinsic region is dimensioned such that upon application of a specific external voltage at the operating temperature of the diode, it is possible for charge carriers to tunnel from one doped region to the other doped region through the intrinsic region. The semiconductor diode has a planar structure on a semiconductor substrate. A semconductor diode of this kind is suitable for use as a protective diode for other components, particularly when they are mounted on substrates consisting fo connecting semiconductors.

Abstract: A 2-transistor cell (26) comprises buried diffused regions (34, 36 and 38) aligned substantially parallel. Floating gates (40) are aligned substantially perpendicular to the diffused regions (34, 36 and 38). A control gate (42) defines a first channel region between first and second diffused regions (34 and 36) to define a read transistor (30) and a second channel region between second and third diffused regions (36 and 38) to define a program transistor. The read transistor (30) and program transistor (32) may be individually optimized according to their respective functions. Further, tunnel windows (70) may be provided for Fowler-Nordheim tunneling.

Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit lines resistivity for a given cell density.

Abstract: An improved bipolar transistor of a BiCMOS integrated circuit is fabricated by utilizing a nitride layer combined with two polysilicon layers to form a self-aligned P-type extrinsic base which results in lower base resistance and lower base-collector capacitance, and thus improved performance.

Abstract: A method of producing a MIS transistor such as a MOS transistor has a P type and an N type channel transistors. P type and N type well regions are provided with the N type and the P type channel transistors, respectively. Both the P type and the N type well regions are covered with an insulating film on which gate electrodes are formed in a predetermined pattern by means of a photo-resist. This photo-resist is used as a channelling block layer when an N type impurity is implanted into the P type well region near the gate electrode so as to form an N type diffusion layer. As a result, the photo-resist prevents the N type impurity from channelling into the gate electrode so that a leak current does not occur within the P type well region of the N type channel transistor.

Abstract: A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

Abstract: For modulating the quantity of gold diffused in a silicon substrate, prior to gold diffusion, one realizes a diffusion of phosphorus varying within a 10.sup.13 to 10.sup.15 atoms/cm.sup.3 range. The concentration of phosphorous is increased at the places where one wishes to increase the gold concentration.

Abstract: Semiconductor processing techniques and devices are provided using a partially opaque ion implantation mask to control the profile of active layers in microwave and millimeter wave monolithic integrated circuits. An N+ layer can be implanted before or after active layer formation. Selection of mask thickness enables control of active channel depth. Adjustment of gate to drain separation in MMIC FETs is also enabled, to control gate to drain voltage. Source to gate series resistance is also controlled. Multiple dielectric layers afford variable mask thicknesses to enable simultaneous formation of differing power level devices monolithically in the same substrate, including low noise high speed devices and power devices. The process and device structure provides enhanced yield, performance, uniformity and reliability.

Abstract: This invention relates to a method of forming a charge coupled device (CCD) channel which has a trench-type multi-potential profile. To form the multi-potential profile, ion implantation is performed several times with a self-alignment mask using a polysilicon layer. This method simplifies the fabrication process and prevents charges from diffusing over the entire CCD channel laterally when the amount of charge is small. This results in charge confinement in a trench in the middle of the channel, enhancing self-induced field and fringing field. Consequently, charge transfer efficiency is improved for small amount of charge.

Abstract: A method of fabricating a semiconductor heterostructure includes the growth of a quantum well active region that is highly lattice-mismatched relative to a substrate. A buffer layer having a thickness above a critical value is grown on the substrate whereby the stress due to a lattice constant mismatch between the buffer layer and substrate is relieved through the formation of misfit dislocations. A strained superlattice structure is grown on the buffer layer in order to terminate any upwardly-propagating dislocations. An unstrained barrier layer is subsequently grown on the superlattice structure. The fabrication method concludes with the growth of a quantum well structure on the unstrained layer wherein a lattice constant mismatch between the quantum well structure and the unstrained barrier layer is smaller than the lattice constant mismatch between the quantum well structure and the substrate.