Patents Examined by Gordon V. Hugo
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Patent number: 5019530Abstract: A method and structures are described for fabricating junctions having metal electrodes separated by polycrystalline barriers with arbitrarily-chosen but controlled barrier height and shape is accomplished by varying the composition and doping of polycrystalline multinary compound semiconductor materials in the barrier, hence varying the Fermi level pinning position such that the Fermi level is fixed and controlled at and everywhere in between the two metal-insulator interfaces. It is known that Schottky barrier heights at metal/compound semiconductor interfaces are determined by a Fermi level pinning mechanism rather than by the electronic properties of the applied metallurgy. The present invention exploits the knowledge that the same type of Fermi level pinning occurs at semiconductor dislocations and grain boundaries. The present invention uses polycrystalline compound semiconductor alloys in which the pinning position is varied over a large range in metal/semiconductor structures.Type: GrantFiled: April 20, 1990Date of Patent: May 28, 1991Assignee: International Business Machines CorporationInventors: Alan W. Kleinsasser, Jerry M. Woodall
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Patent number: 5019520Abstract: A method for preparing a MISFET of a minute size with the channel length of not more than 2 .mu.m between a source and a drain, comprises the steps of forming a mask for exposing a region for forming a well on a planar surface of a semiconductor substrate, and introducing ions at a predetermined energy into the well region by using the mask. The predetermined energy is such as to form a peak of the impurity concentration distribution at a position deeper than the bottom surface of the source and the drain and to maintain the layer of at least a partial layer of the channel at an impurity concentration lower than 10.sup.16 cm.sup.-3 so that a high speed carrier movement in the channel is provided without causing a punch-through phenomenon.Type: GrantFiled: April 30, 1990Date of Patent: May 28, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigeki Komori, Shigeru Kusunoki, Katsuhiro Tsukamoto
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Patent number: 5017508Abstract: A method and apparatus for annealing devices having radiation induced damage is disclosed. A device is exposed to electron irradiation to induce damage to the active area. The device is then annealed with a rapid thermal anneal at a low temperature. The rapid thermal anneal may, optionally, be followed by a conventional oven or furnace anneal at a temperature of about 300.degree. to 450.degree. C. The method produces devices having improved and well controlled characteristics such as short circuit operating area, power dissipated during switching, and on-state voltage drop.Type: GrantFiled: June 29, 1989Date of Patent: May 21, 1991Assignee: Ixys CorporationInventors: Darcy T. Dodt, Walter R. Buchanan
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Patent number: 5015596Abstract: A GaAs JFET according to the present invention is formed as follows. First, an n type active layer is formed on a GaAs substrate. Then, a gate electrode containing a group II element is formed on the n type active layer. With the gate electrode being used as a mask, an n type impurity is ion-implanted in the GaAs substrate with a high concentration in a self-aligned fashion with respect to the gate electrode. Heat-treatment is then performed on the resultant structure to diffuse the group II element in the gate electrode into the n type active layer, forming a p type gate region. At the same time, the ion-implanted n type impurity is activated, forming source and drain regions.Type: GrantFiled: February 8, 1990Date of Patent: May 14, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Nobuyuki Toyoda, Naotaka Uchitomi, Akimichi Hojo
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Patent number: 5013673Abstract: An ion implantation method comprising doping a trench sidewall formed in the surface of a semiconductor substrate, with impurities by intermittently rotating step ion implantation carried out in the state that said sidewall is angled with respect to an ion beam, wherein;the amount of ion implantation to said sidewall is made uniform by varying the scanning velocity of the ion beam on the surface of said semiconductor substrate, at the position near to, and the position distant from, the upstream side of the beam applied to a position at which said surface of semiconductor substrate is inclined with respect to the beam.Also disclosed is a method of manufacturing a semiconductor device making use of such an ion implantation method.Type: GrantFiled: June 26, 1990Date of Patent: May 7, 1991Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Genshu Fuse
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Patent number: 5011784Abstract: A BiCMOS process which provides both isolated and vertical NPN and PNP transistors with better performance characteristics and fewer additional steps than the prior art. The additional steps consist of masked implants with no changes in the thermal steps of the CMOS process. An N-well to contain the vertical PNP transistor is formed during the same step that the NPN vertical transistor collector is formed. The N base of the PNP transistor is formed by implanting an N type material. A P type material is implanted at a high energy of at least 300 keV (150 for doubly ionized Boron) to form a collector of the PNP transistor. A P region is then formed as an emitter of PNP transistor. The high energy P implant gives a peak at approximately 0.8 .mu.m below the surface to form the equivalent of a buried layer (without growing an epitaxial layer after a P implant to form a buried layer as in the prior art).Type: GrantFiled: July 20, 1990Date of Patent: April 30, 1991Assignee: Exar CorporationInventor: Kola N. Ratnakumar
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Patent number: 5011792Abstract: An ohmic contact to III-V semiconductor material comprises substantially eighty to ninety-five percent by weight of tungsten, five to ten percent by weight of antimony, and zero to fifteen percent by weight of indium. The materials are simultaneously sputtered from separate targets in a sputtering reactor.Type: GrantFiled: February 12, 1990Date of Patent: April 30, 1991Assignee: AT&T Bell LaboratoriesInventor: Ranjan Dutta
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Patent number: 5006477Abstract: A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.Type: GrantFiled: November 25, 1988Date of Patent: April 9, 1991Assignee: Hughes Aircraft CompanyInventor: Joseph E. Farb
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Patent number: 4997775Abstract: A method of forming a complementary bipolar transistor device includes the steps of: providing a substrate of semiconductor material including at least two electrically isolated N-type device regions having a generally planar common surface; forming a P-type buried subcollar region in a first of the device regions; forming an N-type buried subcollector region in a second of the device regions; forming an N-type base region in the common surface of the first device region; forming a layer of P-doped polysilicon over the base region in the first device region and over the second device region; patterning the layer of P-doped polysilicon to form an emitter contact generally centered on the base region of the first device region and a generally annular base contact on the second device region; forming a layer of insulating material over the patterned layer of P-doped polysilicon; forming a layer of N-doped polysilicon generally conformally over the device; patterning the layer of N-doped polysilicon to form a basType: GrantFiled: February 26, 1990Date of Patent: March 5, 1991Inventors: Robert K. Cook, Chang-Ming Hsieh, Kiyosi Isihara, Mario M. Pelella
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Patent number: 4997780Abstract: The structure of a pair of concentrically disposed field effect transistors responsive to a common gate electrode, and a process for the fabrication thereof. In one form, a dielectric region is surrounded by an active region of monocrystalline silicon and has situated upon the dielectric region a layer of recrystallized silicon as a second active region. A gate electrode overlies both active regions and serves as a mask to form in such respective regions self-aligned channels. The concentric placement of the active substrate monocrystalline silicon region, and inner perimeter of dielectric, and a further inner active region of recrystallized silicon situated over a dielectric region, facilitates recrystallization from seed of monocrystalline silicon irrespective of the direction of translation taken by the energy beam, and associated melt, in scanning across the structure.Type: GrantFiled: September 21, 1988Date of Patent: March 5, 1991Assignee: NCR CorporationInventors: Nicholas J. Szluk, Jay T. Fukumoto
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Patent number: 4994399Abstract: A method of gettering heavy metal impurities from p-type silicon substrates comprises the prior step of forming an intrinsic gettering layer covered with a surface denuded zone in the silicon substrate by subjecting the substrate to heat treatments which form the intrinsic gettering layer having a large density of crystal microdefects compared to the density of crystal microdefects in the denuded zone; then the step of performing most of the required wafer processes other than the step of forming a metal layer; and subsequently the gettering step of heating the silicon substrate to a predetermined temperature and simultaneously irradiating the substrate with light rays, the predetermined temperature being selected to be within the temperature range 150.degree. C. to 220.degree. C., preferably around 200.degree. C.Type: GrantFiled: May 16, 1990Date of Patent: February 19, 1991Assignee: Fujitsu LimitedInventor: Masaki Aoki
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Patent number: 4994403Abstract: A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective drain regions (30a, 30b), a shared source region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) which may be programmed by hot electron injection and erased by Fowler-Nordheim electron tunneling through respective tunneling oxide windows (40a, 40b) overlying a portion of source region (28) adjacent respective channels (38a, 38b). A wordline or control gate conductor (62) is insulatively disposed adjacent the floating gates (46a, 46b) to program or erase.Type: GrantFiled: December 28, 1989Date of Patent: February 19, 1991Assignee: Texas Instruments IncorporatedInventor: Manzur Gill
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Patent number: 4992387Abstract: A method for fabrication of a field effect transistor includes forming an insulator film of a proper thickness at a predetermined region on one principal surface of a compound semiconductor substrate, forming a gate electrode of a refractory metal on a side wall of the insulator film in a self-alignment manner, and implanting ions with a mask of the insulator film and the gate electrode to form ion implanted regions in the substrate asymmetrically with respect to the gate electrode.Type: GrantFiled: March 20, 1990Date of Patent: February 12, 1991Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Akiyoshi Tamura
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Patent number: 4990461Abstract: A semiconductor integrated circuit device having resistance elements having reduced fluctuation of their resistance values and a fabrication method thereof are disclosed.More definitely, a protective film made of a gate electrode material of MISFETs formed on the main plane of a semiconductor substrate is disposed through an insulator film on the upper surface of the resistance elements comprising a semiconductor region which is formed by introducing an impurity of a first conductivity type into the main plane of the same semiconductor substrate.Type: GrantFiled: July 31, 1989Date of Patent: February 5, 1991Assignee: Hitachi, Ltd.Inventor: Kazunori Onozawa
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Patent number: 4988631Abstract: The present invention, in a photoelectric conversion device including a sensor portion and a thin film transistor portion for the purpose of switching disposed on the same substrate, is manufactured by, first, forming gate electrodes for a thin film transistor portion on the surface of the substrate by a thin film technique, and then, depositing an insulating film, an a-Si film, and electrodes on the insulating substrate so as to be laminated to one after another and commonly covering the sensor portion and the thin film transistor portion, whereby the sensor portion and the thin film transistor portion are enabled to be provided in one series of processing while the device is put in a vacuum chamber.Type: GrantFiled: April 25, 1990Date of Patent: January 29, 1991Assignee: Tokyo Electric Co., Ltd.Inventors: Minoru Ogawa, Koichiro Sakamoto, Toshiyuki Tamura, Kazushige Katsuumi
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Patent number: 4987095Abstract: Unpinned epitaxial metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor are grown by MBE which result in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer is deposited epitaxially in-situ with the compound semiconductor layer which unpins the surface Fermi level. A layer of insulator material is then deposited on the elemental semiconductor layer by PECVD. In one embodiment, the compound semiconductor is GaAs and the elemental semiconductor is Si. The insulator material is a layer of high quality SiO.sub.2. A metal gate is deposited on the SiO.sub.2 layer to form an MOS device. The epitaxial GaAs layer has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO.sub.Type: GrantFiled: June 15, 1988Date of Patent: January 22, 1991Assignee: International Business Machines Corp.Inventors: John Batey, Sandip Tiwari, Steven L. Wright
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Patent number: 4980303Abstract: With a trend toward higher operation speed and higher gain of a Bi-MIS semiconductor device, wherein a bipolar transistor and a MIS FET are formed on the same silicon substrate, a wide bandgap material such as silicon carbide or micro-crystalline silicon is utilized as an emitter material of the bipolar transistor and further a gate electrode of the MIS FET is simultaneously formed using the same wide bandgap material. By applying the above method in the manufacturing of the Bi-MIS semiconductor device, a high amplification factor of the bipolar transistor and a high cutoff frequency of the MIS FET thereof can be easily obtained without additional processes.Type: GrantFiled: August 18, 1988Date of Patent: December 25, 1990Assignee: Fujitsu LimitedInventor: Tunenori Yamauchi
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Method of making a metal-oxide-semiconductor device having shallow source and drain diffused regions
Patent number: 4978629Abstract: A MOS transistor comprises source and drain impurity regions on a surface of a silicon substrate. The source and drain regions have a double diffusion structure including impurity regions of high concentration and impurity regions of low concentration surrounding the high-concentration impurity regions. Outgoing electrode layers of polysilicon are formed on surfaces of the source and drain impurity regions. A gate electrode is formed to partially extend over the outgoing electrode layers for the source and drain impurity regions. The source and drain impurity regions are formed by implanting impurities into the electrode layers and subsequently diffusing the impurities into the semiconductor substrate by thermal diffusion. Those processes of impurity implantation and thermal diffusion are effected after completion of the step of patterning the gate electrode.Type: GrantFiled: September 21, 1989Date of Patent: December 18, 1990Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigeki Komori, Katsuhiro Tsukamoto -
Patent number: 4975382Abstract: A T-shaped gate of an FET is formed by utilizing the image reverse photolithography process, which includes coating of a semiconductor substrate with a positive resist, initial exposure of an resist outside region, reversal baking, flood exposure of the entire resist layer, and development of the resist layer. The image reverse photolithography process is performed after a dummy gate is formed on the semiconductor substrate. By properly adjusting a light quantity of the flood exposure, a resist pattern can be obtained which has a center hole whose boundary surface is inclined inwardly, and whose bottom surface defines a bottom resist layer thinner than the dummy gate. After removing the dummy gate, a gate material is deposited and then the resist pattern is removed to leave the T-shaped gate.Type: GrantFiled: May 11, 1990Date of Patent: December 4, 1990Assignee: Rohm Co., Ltd.Inventor: Satoru Takasugi
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Patent number: 4971931Abstract: In forming integrated circuits on a wafer, diffuser features are provided adjacent to topographic features so that when a film is formed by spin-coating a liquid precursor over the integrated circuits, the action of the spreading liquid relative to the diffuser features in proximity to topographic features minimizes radial streaks which would have been caused by the topographic features.Type: GrantFiled: February 12, 1990Date of Patent: November 20, 1990Assignee: Eastman Kodak CompanyInventors: Armin K. Weiss, Goodwin Ting