Abstract: A semiconductor device 1 has an electrode structure that includes source electrodes 3, a gate electrode 4, and drain electrodes 5 disposed on a semiconductor laminated structure 2 and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings 9, drain wirings 10, and gate wirings 11 disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings 9, the drain wirings 10, and the gate wirings 11 are electrically connected to the source electrodes 3, the drain electrodes 5, and the gate electrode 4, respectively. The semiconductor device 1 includes a conductive film 8 disposed between the gate electrode 4 and the drain wirings 10 and being electrically connected to the source electrodes 3.

Abstract: There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising AlxGa1-xN, wherein 0?x?0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0?y?0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.

Abstract: An inventive solid-state imaging apparatus is provided which can improve the efficiency of the electric carrier transfer from a photoelectric conversion portion to an electric-carrier accumulation portion. The solid-state imaging apparatus includes an active region having the photoelectric conversion portion, the electric-carrier accumulation portion, and a floating diffusion, and an element isolation region having an insulator defining the active region. In planer view, the width of the active region in the electric-carrier accumulation portion under a gate of the first transfer transistor is larger than the width of the active region in the photoelectric conversion portion under the gate of the first transfer transistor.

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.

Abstract: A semiconductor device includes a substrate comprising a layer made of Ge and a semiconductor multilayer structure grown on the layer made of Ge. The semiconductor multilayer structure includes at least one first layer comprising a material selected from a group consisting of AlxGa1-xAs, AlxGa1-x-yInyAs, AlxGa1-x-yInyAs1-zPz, AlxGa1-x-yInyAs1-zNz, and AlxGa1-x-yInyAs1-z-cNzPc, AlxGa1-x-yInyAs1-z-cNzSbc, and AlxGa1-x-yInyAs1-z-cPzSbc, wherein for any material a sum of the contents of all group-III elements equals 1 and a sum of the contents of all group-V elements equals 1. The semiconductor multilayer structure also includes at least one second layer comprising a material selected from a group consisting of GaInAsNSb, GaInAsN, AlGaInAsNSb, AlGaInAsN, GaAs, GaInAs, GaInAsSb, GaInNSb, GaInP, GaInPNSb, GaInPSb, GaInPN, AlInP, AlInPNSb, AlInPN, AlInPSb, AlGaInP, AlGaInPNSb, AlGaInPN, AlGaInPSb, GaInAsP, GaInAsPNSb, GaInAsPN, GaInAsPSb, GaAsP, GaAsPNSb, GaAsPN, GaAsPSb, AlGaInAs and AlGaAs.

Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

Abstract: This application discloses a gate-all-around field effect transistor and a method for manufacturing same.

Abstract: An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.

Abstract: Disclosed is a quantum dot light-emitting diode including a positive electrode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and a negative electrode, wherein the hole injection layer is a p-type oxide semiconductor represented by Formula 1 below: Cu2Sn2-XS3—(GaX)2O3,??[Formula 1] wherein X is greater than 0.2 and less than 1.5 (0.2<x<1.5).

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate, a doped group III-V layer, a gate conductor, a field plate, a first passivation layer, and a second passivation layer. The doped group III-V layer is disposed on the substrate. The gate conductor is disposed on the doped group III-V layer. The field plate is disposed on the gate conductor. The first passivation layer is located between the field plate and the gate conductor. The second passivation layer is located between the field plate and the first passivation layer.

Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

Abstract: The present disclosure relates to a high electron mobility transistor (HEMT) and a fabrication method thereof. The HEMT may include a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a semiconductor gate disposed on the barrier layer; a metal gate disposed on the semiconductor gate, the metal gate having a trapezoidal cross-sectional shape; and a passivation layer directly contacting the metal gate. A first surface of the metal gate contacts a first surface of the semiconductor gate, and an edge of the first surface of the metal gate is located inside an edge of the first surface of the semiconductor gate.

Abstract: A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.

Abstract: In order to reduce costs as well as to effectively dissipate heat in certain RF circuits, a semiconductor device of the circuit can include one or more active devices such as transistors, diodes, and/or varactors formed of a first semiconductor material system integrated onto (e.g., bonded to) a base substrate formed of a second semiconductor material system that includes other circuit components. The first semiconductor material system can, for example, be the III-V or III-N semiconductor system, and the second semiconductor material system can, for example be silicon.

Abstract: A light emitting device includes: a base layer; a first conductive layer on the base layer, and including first and second electrode patterns, and exposing a portion of the base layer at a first area between the first and second electrode patterns; a fine light emitting diode (LED) at the first area; a second conductive layer covering the second electrode pattern and a first side of the fine LED, and contacting the second electrode pattern and the first side of the fine LED; a first insulation layer on the second conductive layer and the fine LED, and partially exposing a second side of the fine LED; and a third conductive layer covering the first electrode pattern and the second side of the fine LED and a portion of a sidewall of the insulation layer, and contacting the first electrode pattern and the second side of the fine LED.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

Abstract: A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.

Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.