Abstract: A display unit having a sufficient luminance and a method of fabricating the display unit are provided. The display unit includes micro-sized semiconductor light emitting devices fixedly arrayed on a plane of a base body of the display unit at intervals. Micro-sized GaN based semiconductor light emitting devices formed by selective growth are each buried in a first insulating layer made from an epoxy resin except an upper end portion and a lower end surface thereof, and electrodes of each of the light emitting devices are extracted. These light emitting devices are fixedly arrayed on the upper plane of the base body at intervals. A second insulating layer made from an epoxy resin is formed on the plane of the base body so as to cover the semiconductor light emitting devices each of which has been buried in the first insulating layer.

Abstract: Methods are apparatuses are disclosed for a software tool adapted to function with at least library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: A system and method is described for fabricating microcomponents onto pre-existing integrated electronics. One embodiment of the present invention provides additional process steps after completion of all electronics fabrication that may etch trough the oxide of any passivation layer that may be there to the single crystal silicon (SCS) of a silicon on insulator (SOI) integrated circuit. Once at the SCS level of the existing wafer, any number of microcomponents, such as connectors, receptacles, handles, tethers, and the like may preferably be fabricated onto the chip using relatively low temperature and inexpensive processing; thus, preferably preserving the integrity of the preexisting electronics.

Abstract: A manufacturing method of an active matrix substrate which can prevent the complexity of manufacturing processes, widens the range of material choice and allows high manufacturing yield, and a manufacturing method of a liquid crystal display using such active matrix substrate. Conductive colored layers (606 to 608) functioning as pixel electrodes and color filters are formed by a process of discharging, by an ink jet method, a mixed ink of coloring material and conductive material to the formation area of a pixel electrode to be connected electrically to an active element (602).

Abstract: In a method of manufacturing matrix electron emitter arrays, each array comprising a plurality of scanning lines formed on a glass substrate and arranged in parallel with each other, a plurality of signal lines formed in a direction to cross the scanning lines and arranged in parallel with each other, and field-emission type electron emitters formed in the pixel areas which are arranged at the intersections of the scanning lines and the signal lines, a pulse voltage with a specific polarity and another pulse voltage with the reverse polarity are applied to any two of the scanning lines and current is caused to flow through electron emitters connected in series-via a signal line, thereby subjecting the conductive thin film constituting an electron emitter to a conductive activation process for forming an electron emitting section.

Abstract: The present invention relates to etching for removing a carbon thin film formed on a surface of a sample, to prevent a damage on a sample and eliminate the necessity of providing a special device (such as vacuum pump) as is required in plasma etching. A sealed reaction chamber 100A in which a sample 500 formed with a carbon thin film 510 on its surface is to be set, a gas feed means 200A for feeding argon gas which is an inert gas Ar into which a predetermined proportion of oxygen gas O2 has been mixed from one end to the interior of the reaction chamber 100A, an exhaust means 300A for discharging carbon dioxide gas CO2 from the downstream side of the inert gas Ar fed from the gas feed means 200A, and a heating means 400A for heating the sample 500 to 550° C. or higher are provided.

Abstract: A method for fabricating a non-FLASH integrated circuit that minimizes Vmin shift. A protective overcoat (134) is deposited to protect and encapsulate the top metal interconnect layer (118). The protective overcoat (134) is patterned and etched to form bondpad windows either before or after depositing the final metal interconnect layer (136). A sinter that is normally performed after forming the bondpad windows is either omitted or the temperature of the sinter is kept at or below 350° C.

Abstract: In one aspect, the invention includes a method of forming a, silicon dioxide layer, including: a) forming a high density plasma proximate a substrate, the plasma including silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an, etch rate; a ratio of the deposition rate to the etch rate being at least: about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C.

Abstract: A stackable semiconductor package having a lead frame, a plurality of electrical paths, and a sealing material. The leadframe has a plurality of leads, each one of the plurality of leads having a top portion exposed to a top surface of the semiconductor package and a bottom portion resting flush with a bottom surface of the semiconductor package. In this manner, the leads extending from the top surface to the bottom surface of the semiconductor package provide an electrical path for connecting and electrically powering a second semiconductor package stacked on top of a first bottom semiconductor package.

Abstract: Methods and apparatus are provided for plasma doping and ion implantation in an integrated processing system. The apparatus includes a process chamber, a beamline ion implant module for generating an ion beam and directing the ion beam into the process chamber, a plasma doping module including a plasma doping chamber that is accessible from the process chamber, and a wafer positioner. The positioner positions a semiconductor wafer in the path of the ion beam in a beamline implant mode and positions the semiconductor wafer in the plasma doping chamber in a plasma doping mode.

Abstract: A microelectronic package including at least one microelectronic die disposed within an opening in a microelectronic package core, wherein a liquid encapsulation material is injected with a dispensing needle within portions of the opening not occupied by the microelectronic dice. The encapsulation material is cure thereafter. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic package core to form the microelectronic package.

Abstract: First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pad and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed.

Abstract: Methods are provided for identifying root causes of particle issues and for developing particle-robust process recipes in plasma deposition processes. The presence of in situ particles within the substrate processing system is detected over a period of time that spans multiple distinct processing steps in the recipe. The time dependence of in situ particle levels is determined from these results. Then, the processing steps are correlated with the time dependence to identify relative particle levels with the processing steps. This information provides a direct indication of which steps result in the production of particle contaminants so that those steps may be targeted for modification in the development of particle recipes.

Abstract: A method for manufacturing a semiconductor device having a non-volatile memory transistor may include the steps of forming a floating gate 22 over a semiconductor layer 10 through a first insulation layer 20, forming a second insulation layer 26 that contacts the floating gate 22, forming a control gate 28 over the second insulation layer 26, forming a source region 14 and a drain region 16 in the semiconductor layer 10, depositing a insulation layer 40 over the semiconductor layer 10, and etching the insulation layer 40 to form a sidewall insulation layer, wherein the etching of the insulation layer 40 is conducted such that the insulation layer 40 remains above the floating gate 40, and the floating gate 22 is not exposed.

Abstract: A method for processing a semiconductor wafer or similar article includes the step of spinning the wafer and applying a fluid to a first side of the wafer, while it is spinning. The fluid flows radially outwardly in all directions, over the first side of the wafer, via centrifugal force. As the fluid flows off of the circumferential edge of the wafer, it is contained in an annular reservoir, so that the fluid also flows onto an outer annular area of the second side of the wafer. An opening allows fluid to flow out of the reservoir. The opening defines the location of a parting line beyond which the fluid will not travel on the second side of the wafer. An apparatus for processing a semiconductor wafer or similar article includes a reactor having a processing chamber formed by upper and lower rotors. The wafer is supported between the rotors. The rotors are rotated by a spin motor. A processing fluid is introduced onto the top or bottom surface of the wafer, or onto both surfaces, at a central location.

Abstract: Various methods are provided of forming capacitor electrodes for integrated circuit memory cells in which out-diffusion of dopant from doped silicon layers is controlled by deposition of barrier layers, such as layers of undoped silicon and/or oxide. In one aspect, a method of forming hemispherical grain silicon on a substrate is provided that includes forming a first doped silicon layer on the substrate and a first barrier layer on the doped silicon layer. A hemispherical grain polysilicon source layer is formed on the first barrier layer and a hemispherical grain silicon layer on the hemispherical grain polysilicon source layer. By controlling out-diffusion of dopant, HSG grain size, density and uniformity, as well as DRAM memory cell capacitance, may be enhanced, while at the same time maintaining reactor throughput.

Abstract: A method of forming a cell memory structure including the step of planarizing an HDP/LDP oxide layer lying over a capacitor area. The method provides for the planarization of the cell storage node, good isolation between the transistor and storage node, reduced step height for the cell-transistor and has the potential for increasing the node capacitance (like DRAM storage node).

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.

Abstract: A system for processing a workpiece includes a base having a bowl or recess for holding a liquid. A process reactor or head holds a workpiece between an upper rotor and a lower rotor. A head lifter lowers the head holding the workpiece into contact with the liquid. The head spins the workpiece during or after contact with the liquid. The upper and lower rotors have side openings for loading and unloading a workpiece into the head. The rotors are axially moveable to align the side openings.

Abstract: A system and method are disclosed which constrain a microcomponent that is totally released from a substrate for handling of such totally released microcomponent. A preferred embodiment provides a system and method which constrain a totally released microcomponent to a base (e.g., another microcomponent or a substrate). For example, a preferred embodiment provides constraining members that work to constrain a microcomponent to a substrate as such microcomponent is totally released from such substrate. Accordingly, such constraining members may aid in preserving the microcomponent with its substrate during the release of such microcomponent from its substrate during fabrication. Additionally, a preferred embodiment provides constraining members that are suitable for constraining a totally released microcomponent to a base for post-fabrication handling of the microcomponent.