Abstract: Disclosed is a semiconductor device 1 comprising: a semiconductor chip 10; a multilayer wiring structure 30 stacked on the semiconductor chip 10; and an electronic component 60,80 embedded in the multilayer wiring structure 30.

Abstract: A high frequency switch module includes a multilayer substrate and a switch IC. The switch IC is mounted on a top plane of the multilayer substrate. A drive power signal input port and control signal input ports are connected to direct current external input ports through direct current voltage conductors, respectively. In-layer conductors of the direct current voltage conductors are arranged so that the in-layer conductors overlap each other at least partially in a state in which the multilayer substrate is viewed along a stacking direction.

Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Abstract: This invention provides an array substrate, a method for fabricating the same, and an OLED display device. Each pixel unit of the array substrate comprises: a TFT drive layer; an OLED further away from the substrate than the TFT drive layer and driven by it, the OLED sequentially comprises a first electrode, a light emitting layer, a second electrode, wherein the first electrode is transparent, and the second electrode is a transflective layer, or the second electrode is transparent and has a transflective layer disposed thereon; a reflection layer disposed between the TFT drive layer and the OLED and forming a microcavity structure with the transflective layer, and a reflective surface of the reflection layer has a concave-convex or corrugated structure disposed thereon for causing diffuse reflection of light; and a color filter film disposed between the reflection layer and the OLED and located in the microcavity structure.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming, on a principal face of a substrate, a semiconductor layer including a first semiconductor region of a first conductivity type; and forming, in the semiconductor layer, a trench having a bottom located in the first semiconductor region. The method further includes a step of forming a trench bottom impurity region being of a second conductivity type and covering the bottom of the trench by performing annealing to cause part of the semiconductor layer corresponding to an upper corner portion of the trench to move to be placed on the bottom of the trench.

Abstract: A method for manufacturing a semiconductor laser element includes forming an etching end point detection layer on part of a substrate, forming an substrate exposed portion and forming a lower cladding layer, an active layer, and an upper cladding layer on the etching end point detection layer and on the exposed portion, forming an insulating film pattern at a distance corresponding to a clearance region, from directly above a boundary between the substrate exposed portion and the etching end point detection layer, etching the upper clad layer, the active layer, and the lower cladding layer using the insulating film pattern as a mask and stopping etching at a time when the etching end point detection layer is exposed or after a predetermined time duration after the time.

Abstract: A method for fabricating a multiple MEMS device. A semiconductor substrate having a first and second MEMS device, and an encapsulation wafer with a first cavity and a second cavity, which includes at least one channel, can be provided. The first MEMS can be encapsulated within the first cavity and the second MEMS device can be encapsulated within the second cavity. These devices can be encapsulated within a provided first encapsulation environment at a first air pressure, encapsulating the first MEMS device within the first cavity at the first air pressure. The second MEMS device within the second cavity can then be subjected to a provided second encapsulating environment at a second air pressure via the channel of the second cavity.

Abstract: The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 ?.

Abstract: An optical semiconductor unit of the present invention has an LED device provided with an LED (Light Emitting Diode) and a socket to which the LED device is mounted, the LED device has a main body to which the LED is mounted, the main body has a first surface to which block-shaped electrode portions are connected.

Abstract: A thin film transistor array panel includes a substrate; a gate line located over the substrate and including a gate pad portion; a data line located over the gate line and including a source electrode and a data pad portion; a drain electrode; a first passivation layer located over the data line and the drain electrode; an organic insulating layer located over the first passivation layer and having a contact hole; a first field generating electrode located over the organic insulating layer and having an opening; a second passivation layer located over the first field generating electrode; and a second field generating electrode located over the second passivation layer. The contact hole coincides with or is smaller than the opening, and the contact hole has a tapered structure.

Abstract: An organic light emitting diode display includes a substrate having organic light emitting diodes thereon. A thin film encapsulation layer is formed on the substrate such that the thin film encapsulation layer covers the organic light emitting diodes. A nonorganic layer is formed under the thin film encapsulation layer along the edge of the thin film encapsulation layer.

Abstract: A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade.

Abstract: Provided is a liquid crystal display device, in which: the gate lines include a first gate line and a second gate line for respectively outputting the scanning signals at two different scanning timings for each of scanning lines; and a unit pixel for color display, constituted by three pixels corresponding to a red (R) pixel, a green (G) pixel, and a blue (B) pixel arranged side by side, is formed in a region surrounded by the first gate line, the second gate line, and the drain lines, and the three pixels corresponding to the red (R) pixel, the green (G) pixel, and the blue (B) pixel are arranged in matrix for the each unit pixel.

Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.

Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.

Abstract: A semiconductor device includes an interposer mounting a semiconductor chip. The interposer includes a silicon substrate having a recessed region formed on a first surface, a first through via penetrating a first region of the silicon substrate from the first surface to an opposing second surface, an insulator disposed in the recessed region, and a first wire pattern at least partially disposed on the insulator and electrically connecting the first through via to the semiconductor chip.

Abstract: The present invention supplies a manufacturing method of a semiconductor device, which includes a non-contact inspection process capable of confirming if a circuit or circuit element formed on an array substrate is normally performed and can decrease a manufacturing cost by eliminating wastes to keep a defective product forming. An electromotive force generated by electromagnetic induction is rectified and shaped by using primary coils formed on a check substrate and secondary coils formed on an array substrate, whereby a power source voltage and a driving signal are supplied to circuits or circuit elements on a TFT substrate so as to be driven.

Abstract: In an example of a method for controlling the formation of dopants in an electrically actuated device, a predetermined concentration of a dopant initiator is selected. The predetermined amount of the dopant is localized, via diffusion, at an interface between an electrode and an active region adjacent to the electrode. The dopant initiator reacts with a portion of the active region to form the dopants.

Abstract: Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit production facilities. Measuring profiles of structures with many elements in integrated circuits, such as MOS transistor gates with recessed regions for Si—Ge epitaxial layers, is not cost effective for the commonly used metrology techniques: SEM, TEM and AFM. Scatterometry is technically unfeasible due to the number of elements and optical constants. The instant invention is a simplified scatterometry structure which reproduces the profiles of a structure to be profiled in a simpler structure that is compatible with conventional scatterometric techniques. A method of fabricating a transistor and an integrated circuit using the inventive simplified scatterometry structure are also disclosed.

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.