Abstract: A dynamic aperture is disclosed. A dynamic aperture includes a base layer, a conductive structure disposed on the base layer, and a layer of a material having a dynamically controllable electrical conductivity that is disposed over the base layer and the conductive structure. A transmission profile of the dynamic aperture is determined by a combination of the conductive structure and the layer of the material. The transmission profile is dynamically alterable by controlling the electrical conductivity of the layer of the material.

Abstract: A product-sum operation device includes a product operator and a sum operator. The product operator includes a plurality of variable-input product operation elements and a plurality of fixed-input product operation elements. Each of the plurality of variable-input product operation elements and the plurality of fixed-input product operation elements and is a resistance change element. The product-sum operation device includes variable input units and that input a variable signal to a plurality of variable-input product operation elements and fixed input units and that input a determined signal to the plurality of fixed-input product operation elements and in synchronization with the variable signal. The sum operator includes an output detector that determines the sum of outputs from the plurality of variable-input product operation elements and outputs from the plurality of fixed-input product operation elements.

Abstract: Methods and systems for controlling a multipurpose power converter for converting power for a transport climate control system are provided. The multipurpose power converter includes a rectifier having a first leg, a second leg, and a third leg. The multipurpose power converter also includes a first switch, a second switch, and an inductor-capacitor network. The first switch and the second switch are connected to the third leg. The inductor-capacitor network is connected to the first switch. When the first switch is on and the second switch is off, the multipurpose power converter is configured as a single-phase AC power converter. When the first switch is off and the second switch is on, the multipurpose power converter is configured as a three-phase AC power converter.

Abstract: A semiconductor switch device includes a switchable power semiconductor and a control circuit. The semiconductor switch device has a current sink and a current amplifier designed to amplify during a switching process a partial current of the total current flowing across the control capacitor that is not discharged by the current sink up to an adjustable maximum current and to apply the amplified partial current to the control electrode of the power semiconductor so as to counteract the change in the voltage across the collector-emitter path or the drain-source path of the power semiconductor during the switching process. An additional circuit provides an adapted switch-on transition by smoothing the collector voltage and/or the drain voltage of the switchable power semiconductor when switching over the collector-emitter path or the drain-source path of the power semiconductor from a blocked state into a conductive state.

Abstract: A window type watchdog timer includes a frequency dividing circuit for generating a frequency-divided clock signal by dividing a frequency of a reference clock signal; a monitoring circuit for monitoring occurrence of a first error in which clear control from a target device is interrupted for a first time or more, and occurrence of a second error in which an interval between two consecutive clear controls from the target device is shorter than a second time shorter than the first time, based on the frequency-divided clock signal; and outputting an error signal when the first error or the second error is detected; and a setting circuit for variably setting the first time and the second time by variably setting a frequency division ratio in the frequency dividing circuit and variably setting a detection condition of the first error and the second error.

Abstract: The invention relates to a method for determining a time of a flank in a signal, wherein the method comprises a step of reading the signal and has a master clock rate for operating a digital evaluation unit for evaluating the time of the flank. The method also comprises a step of forming a data word representing the signal, using a deserializer of a SERDES cell, wherein the data word has a plurality of bits, and wherein a sampling clock rate is applied to the SERDES cell for sampling the signal, which sampling clock rate is higher than the master clock rate, wherein one flank or two flanks of the sampling clock rate are used for sampling the signal. Finally, the method comprises a step of determining the time of the flank in the signal using the data word and the master clock rate in the evaluation unit.

Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.

Abstract: Systems and methods for monitoring poultry house egg production. The system includes: a conveyor for conveying poultry eggs; at least one laser sensor directed in direction of said conveyor for measuring distance of said conveyor's surface and poultry eggs conveyed thereupon; a computer coupled with said at least one lase sensor; wherein, number of poultry eggs passed through said conveyor at a given moment is determined by identifying and analyzing fluctuations in measured distance from said at least one laser sensor.

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Abstract: Gate drivers and auto-zero comparators are disclosed. An example integrated circuit includes a transistor comprising a gate terminal and a current terminal, a gallium nitride (GaN) gate driver coupled to the gate terminal, the GaN gate driver configured to adjust operation of the transistor, and an enhancement mode GaN comparator coupled to at least one of the transistor the GaN gate driver, the enhancement mode GaN comparator configured to compare a voltage to a reference voltage, the voltage based on current from the current terminal, the GaN gate driver configured to adjust the operation of the transistor based on the comparison.

Abstract: A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops includes multiple phase-locked loops, a data selector and a signal synthesizer. In a case of generating a clock signal with low jitter, output signals of two phase-locked loops are adjusted to be the same in frequency and phase, and output signals of other phase-locked loops are adjusted to be different from each other in frequency. The data selector selects output signals, and the signal synthesizer is enabled to superimpose and then average the first and second selected output signals, so as to obtain a clock signal with jitter eliminated. In a case of generating multiple clock signals with different frequencies, output signals of the multiple phase-locked loops are adjusted to be different from each other in frequency, to obtain multiple clock signals with different frequencies through the data selector without enabling the signal synthesizer.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: A control system of a marine vessel includes a portable device and a receiving device. The portable device transmits a switch control signal to the receiving device based on an input operation. The control system of the marine vessel performs an authentication control process based on an authentication signal from the portable device, and controls opening or closing of a current path based on the switch control signal from the portable device.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: A current blocking element is provided. The current blocking element includes a first electrode layer, an ion conductive layer, and a second electrode layer, which are laminated in this order, wherein the first electrode layer is configured to hold ions; the ion conductive layer has ionic conductivity and does not have electronic conductivity; and the second electrode layer is configured to hold ions. Ions held in the first electrode layer are moved to the second electrode layer when current is configured to flow between the first electrode layer and the second electrode layer. Current flow between the first electrode layer and the second electrode layer is blocked when ions held in one of the first and second electrode layers are depleted saturated.

Abstract: Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

Abstract: The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.

Abstract: Disclosed are computer-implemented techniques for providing immediate feedback to rowers for training and other activities to improve competitiveness of rowing crews. The techniques include a computing device receiving from a set of stroke unit devices, data that represent changes in acceleration of users' seats corresponding to users' strokes, receiving reference stroke data corresponding to a reference user's stroke, and generating from the received data from the set of stroke unit devices and the received reference strokes data, feedback data that correspond to relative stroke timing differences of each of the users, relative to the reference stroke, and transmitting the generated feedback data to user devices according to a feedback mechanism. Various feedback mechanisms are disclosed including visual, audio and tactical feedback mechanisms.