Abstract: A triple modular redundancy (TMR) flip-flop includes a set of master-gate-latch circuits including a first set of inputs to receive a first digital signal, and a second set of inputs to receive a clock; and a voting logic circuit including a set of inputs coupled to a set of outputs of the set of master-gate-latch circuits, and an output to generate a second digital signal based on the first digital signal. Another TMR flip-flop includes a set of master-gate-latch circuits to receive a set of digital signals in response to a first edge of a clock, respectively; and latch the set of digital signals in response to a second edge of the clock, respectively; and a voting logic circuit to receive the latched set of digital signals; and generate a second digital signal based on a majority of logic levels of the latched first set of digital signals, respectively.

Abstract: A variable filter and method of switching a resonant frequency of the variable filter from an initial frequency to a desired frequency, where the variable filter has a tunable frequency and a variable Q. With the variable filter operating at the initial frequency and an initial Q, the variable filter is Q-spoiled toward a low-Q state. The variable filter is tuned toward the desired frequency and the tunable resonator is Q-enhanced from the low-Q state to achieve a desired filter response.

Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.

Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.

Abstract: Disclosed is an electronic device that is configured to determine whether a phase locked loop (PLL) circuit is operating normally, thereby preventing component damage in the electronic device and preventing disconnection from a communication network.

Abstract: Methods, apparatus, systems and articles of manufacture are described to parallelize transistors. An example apparatus includes a first transistor on a first die and a second transistor on a second die. The example apparatus includes a parallel feedback terminal coupled to the first die and the second die and a current sensor including a first contact and a second contact. The example apparatus includes a resistor coupled to the current sensor and at least one of the switched terminal or a ground terminal. The example apparatus includes an active drive controller including a first input coupled to the resistor, a second input coupled to the parallel feedback terminal, and an output coupled to the parallel feedback terminal. The example apparatus includes an edge delay controller adapted to be coupled to a gate driver and an error amplifier, and a control contact adapted to be coupled to the gate driver.

Abstract: A method for capacitive touch sensing with high safety integrity includes measuring at least one of a first mutual-capacitance of an electrode pair comprising two of a first electrode, a second electrode and a third electrode, and a self-capacitance between the third electrode and a body biased to a fixed voltage. A contact of the body to a dielectric overlaying each of the first electrode, the second electrode and the third electrode is detected by comparing at least one of the first mutual-capacitance of the electrode pair to a first reference range, and the self-capacitance to a second reference range.

Abstract: A reference voltage generator includes an input terminal configured to receive an enable signal and an output terminal configured to provide an output signal. A voltage generator circuit is arranged to generate a first output voltage signal, and a pre-settling circuit is arranged to generate a second output voltage. The pre-settling circuit is configured to provide the second output voltage signal at the output terminal in response to the enable signal received at the input terminal, and following a first time period provide the first output voltage at the output terminal.

Abstract: Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.

Abstract: Described herein are multiple designs for an improved analog switch for use in transmitting high voltage signals without using high voltage power supplies for the switch. The analog switches are able to pass and block input signals in the approximate range of ?100 V to +100 V. The use of translinear loops and a bootstrap configuration results in a constant on-resistance of the symmetrical switches and matches the conductance of each analog switch to the transconductance of an NMOS transistor, which can be easily stabilized with a constant gm biasing scheme. In certain embodiments, a shunt termination (T-switch) configuration is used for better off-isolation, and each of the symmetrical switches has its own translinear loop and thus flexibility of on-resistance and termination voltage.

Abstract: An active two-terminal capacitor device with a controllable capacitance based on a capacitance value input C_I. A processor system PRS executes an algorithm which controls a power converter PCV with controllable electric switches connected to the two external terminals A, B along with a fixed value capacitor component CI. Based on sampling of at least the voltage across the capacitor component CI, the algorithm controls the power converter PCV to provide a resulting capacitance across the external terminals A, B which serves to match the capacitance value in ut C_I.

Abstract: According to an aspect, a power supply is provided. The power supply includes a plurality of voltage converters including a first voltage converter and one or more other voltage converters. The power supply also includes a power supply control configured to perform a plurality of operations including enabling the first voltage converter during a start-up mode of operation, monitoring and regulating an output of the first voltage converter, reconfiguring the power supply control to enable the one or more other voltage converters based on determining that the output of the first voltage converter meets a regulation threshold, and transitioning from the start-up mode of operation to a regular mode of operation based on enabling the one or more other voltage converters to output one or more regulated voltages by the power supply.

Abstract: In a general aspect, a circuit can include a pass device configured to receive an input voltage and provide an output voltage. The circuit can further include a current sink coupled with a control terminal of the pass device, the current sink being configured to discharge the control terminal of the pass device to limit the output voltage in response to the input voltage exceeding a threshold voltage. The circuit can also include a switch coupled in series with the current sink, the switch being configured to enable the current sink in response to the input voltage exceeding the threshold voltage.

Abstract: A reference voltage generating circuit includes: an operational amplifier including a first input terminal connected to a first node and a second input terminal connected to a second node; a first transistor connected between a ground terminal and the first node, wherein a first current flows in the first transistor; a second transistor connected to the ground terminal; and a first variable resistor connected between the second transistor and the second node, wherein the first variable resistor has a first resistance value for adjusting the first current, based on a change in a current characteristic of the first transistor caused by a variation in a process of forming the first transistor. The reference voltage generating circuit provides a reference voltage, based on a voltage of the first node and a voltage across the first variable resistor.

Abstract: In certain aspects, a driver includes a pull-down transistor coupled between an output and a ground, a pull-up n-type field effect transistor (NFET) coupled between a first voltage rail and the output, and a pull-up p-type field effect transistor (PFET) coupled between the first voltage rail and the output. The driver also includes a first switch coupled between a gate of the pull-up NFET and the ground, and a second switch coupled between a gate of the pull-up PFET and a second voltage rail.

Abstract: Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.

Abstract: A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports or the state of the one or more output ports change upon determining the states have been stable for the preset number of the cycles.

Abstract: An inverter for wireless power transfer includes a primary inverter connected in series with a first primary inductor. A first primary capacitor is connected in parallel with the first primary inductor and primary inverter. A series-connected second primary capacitor and primary pad inductor are in parallel with the second primary capacitor. The synchronous inverter includes a controller configured to detect a first primary current in the first primary inductor to control switches in the primary inverter to provide a positive primary inverter voltage across the output of the primary inverter in response to detecting a positive first primary current, and control the switches in the primary inverter to provide a negative primary inverter voltage across the output of the primary inverter in response to detecting a negative first primary current.

Abstract: An integrated circuit according to an embodiment of the disclosure may include a plurality of function blocks, a spread spectrum clock (SSC) generator that generates a spread spectrum clock based on a frequency modulation rate value, a clock distribution circuit that distributes the generated spread spectrum clock into the plurality of function blocks, a memory that stores predetermined frequency modulation rate values respectively corresponding to the plurality of function blocks, and a control circuit, and the control circuit may be configured to generate the spread spectrum clock based on a smaller frequency modulation rate value among a first frequency modulation rate value and a second frequency modulation rate value respectively corresponding to a first function block and a second function block, which are operating, from among the plurality of function blocks. Moreover, various embodiment found through the present disclosure are possible.

Abstract: A system for performing a phase control operation includes: an internal clock generation circuit configured to generate an internal clock by delaying a clock by a first delay variation, and generate a reference clock by delaying the clock by a second delay variation, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variation which is controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.