Abstract: Disclosed is a signal processing circuit, a contactless connector, a signal processing method and a storage medium.

Abstract: A communication device mounted in each of a plurality of information processing devices connected to a fabric, the communication device comprises: a serial interface that transmits and receives a first packet compliant with a Peripheral Component Interconnect Express (PCIe) standard; a requester unit that acquires the first packet from the serial interface and converts the first packet that has been acquired into a second packet that is transmitted and received via the fabric among a plurality of the information processing devices sharing a memory space that is virtually extended by using a device identifier specific to each of the information processing devices; a fabric communication unit that transmits and receives the second packet via the fabric; and a completer unit that acquires the second packet from the fabric communication unit and generating a response packet to a request included in the second packet that has been acquired.

Abstract: An audio and video transmission system includes a multimedia device. The multimedia device includes a high-definition multimedia interface (HDMI) receiver, a first transfer circuit, and a first universal serial bus type C (USB-C) interface. The first transfer circuit is configured to transfer a first audio signal output by an audio channel pin of the HDMI receiver into a second audio signal in a universal serial bus (USB) interface format. The first USB-C interface is configured to transmit the second audio signal. The HDMI audio channel pin is an audio return channel (ARC) pin or an enhanced ARC pin.

Abstract: An overlap detection unit for a user station of a serial bus system. The overlap detection unit includes a collision detection block for detecting bus states on a bus of the bus system, in which, in order to transmit a message, bus states of user stations of the bus system are generated on the bus with a first physical layer in a first communication phase, and are generated with a second physical layer in a second communication phase, the second physical layer being different from the first physical layer. The collision detection block generates a signal whose value indicates whether or not the bus states in the second communication phase have a level that corresponds to an overlap of the first and second physical layers or an overlap of two second physical layers, and the collision detection block is designed to output the signal for the user station.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a secure area and a non-secure area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a secure mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: The invention relates to a bus-capable device having an input interface and an output interface for connecting to a serial bus, particularly a CAN bus, wherein the input interface and the output interface each have at least one signal line connection, and further having a terminating resistor for terminating the bus and a switch apparatus for switching the terminating resistor active as a function of the connection status of the input and output interfaces, wherein the input interface and the output interface each having a supply voltage connection for providing a supply voltage to the output and/or input interfaces of a respective next bus-capable device and a feedback connection for receiving the supply voltage from an output and/or input interface of a respective next bus-capable device, wherein the switch apparatus has an evaluation circuit for determining the presence of the supply voltage at the feedback connections of the input and output interfaces and an activation circuit for switching the terminati

Abstract: Methods and servers for storing data associated with users and digital items of a recommendation system having access to non-distributed and distributed storages. The server trains a model based for generating first user and item embeddings. The server stores (i) the first user embeddings in the non-distributed storage, and (ii) the first item embeddings in the distributed storage. The server re-trains the model for generating second user and item embeddings. The server stores (i) the second user embeddings in the non-distributed storage in addition to the first user embeddings, and (ii) second item embeddings in the distributed storage instead of the respective first item embeddings by replacing the respective first item embeddings. When the second item embeddings are stored on each node of the distributed storage, the server removes the first user embeddings associated with the first value from the non-distributed storage.

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

Abstract: In some embodiments, a system for communicating USB information via an extension medium is provided. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The UFP device is communicatively coupled to a host device via a USB-compliant connection. The DFP device is communicatively coupled to at least one USB device via a USB-compliant connection and communicatively coupled to the UFP device via a non-USB extension medium. The DFP device is configured to receive, from the UFP device, an incoming request packet addressed to a first USB endpoint provided by a USB device; and hold transmission of an outgoing request packet based on the incoming request packet to the USB device in response to determining that a ping response packet has not yet been received from the first USB endpoint.

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

Abstract: A communication control device for a user station for a serial bus system. The communication control device controls a communication of the user station with at least one other user station of the bus system, and generates a transmission signal for transmission onto a bus of the bus system and/or to receive a signal from the bus. The communication control device generates the transmission signal according to a frame in which bits having a predetermined temporal length are provided. The communication control device is designed to shorten, in comparison to some other bit of the bit sequence, at least one bit in the frame that is situated in a bit sequence of at least two bits having the same logical value, and the communication control device is designed to not shorten bits that are not situated in a bit sequence of at least two bits having the same logical value.

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

Abstract: A SCO containing a single unified motherboard is generally described. The SCO includes a touchscreen display configured to provide a visible display for interaction with a user. The SCO also has a built-in scanning capabilities within the motherboard and connectors to connect to the display and other components of the SCO. The motherboard includes a multicore processor configured to control the scanning, the display and the other components. The scanning capability is configured to scan an item for a symbol, detect the presence of the symbol on the item, identify information on the symbol related to the item, and control the display to display an identity, price of the item, and print a receipt for a customer.

Abstract: A thunderbolt device module is provided. The thunderbolt device module of the invention includes a first interface protocol component, a thunderbolt controller and a second interface protocol component. A root complex of an electronic device is via a bus, conforming to a PCIe interface protocol, directly or indirectly electrically coupled to the second interface protocol component. The first interface protocol component and the second interface protocol component both conform to a predetermined interface protocol. In particular, the predetermined interface protocol is not the PCIe interface protocol, but supports the PCIe interface protocol. The thunderbolt controller is electrically coupled to the first interface protocol component. The second interface protocol component is electrically coupled to the first interface protocol component. The communication between the second interface protocol component and the first interface protocol component conforms to the predetermined interface protocol.

Abstract: A Secured Keyboard Video and Mouse (SKVM) system for selectively controlling a plurality of individual computers by a single set comprising a keyboard, a pointing device and at least one video monitor (in some cases, can be controlled also by computer), the SKVM comprising separate electrical circuits for transmitting the display sources, the pointing device and keyboard communications.

Abstract: A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is coupled to a DP sink device through a DP connector. The USB core circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit supports only one specific conduction mode that only allows transmitting DP signals between the USB interface circuit and the DP interface circuit.

Abstract: An information handling system includes a USB-C port, first and second processors, and a USB-C power delivery controller. The first processor couples to the USB-C port utilizing a first connection type. The second processor couples to the USB-C port utilizing a second connection type. The USB-C power delivery controller includes first registers associated with the first processor and second registers associated with the second processor. The first processor utilizes the first registers to communicate with the USB-C port. The second processor utilizes the second registers to communicate with the USB-C port.

Abstract: A scramble and descramble hardware implementation method based on data bit width expansion. After expansion, redundant terms are eliminated, and scramble/descramble operation results within the current operation cycle and the value of the shift register after shifting are calculated at once. The present method exhibits advantageous effects with respect to the scramble and descramble polynomial defined by USB3.1 and PCI-Express3.0 protocols, and can obtain a relatively small hardware delay, so that the system can work at a higher frequency.

Abstract: A system of electronic modules is described, along with a method of assigning addresses to the modules. The modules are communicatively connected along a communication path, and are also communicatively connected to an address bus. Adders are positioned along the address bus, with at least one adder located between each pair of modules. When any module is assigned an address, its adjacent adder will increment the address and assign the incremented address to the next-adjacent module.