Patents Examined by Harry Z Wang
-
Patent number: 11748289Abstract: A system includes a bridge circuit configured for low latency communication among integrated circuits (ICs). The bridge circuit includes a plurality of transceiver circuits. Each transceiver circuit is coupled to a corresponding parallel channel in the IC. Each transceiver circuit is configured to send and receive data over the corresponding parallel channel. Each transceiver circuit includes a transmit channel configured to packetized data received from the corresponding parallel channel for transmission over a serial link to a second IC. Each transceiver circuit includes a receive channel configured to depacketize data received from the serial link from the second IC. The serial link is asynchronous to each of parallel channel coupled to the first bridge circuit.Type: GrantFiled: November 16, 2021Date of Patent: September 5, 2023Assignee: Xilinx, Inc.Inventors: Michael Chyziak, Raghukul B. Dikshit
-
Patent number: 11741041Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.Type: GrantFiled: February 10, 2022Date of Patent: August 29, 2023Assignee: APPLE INC.Inventors: Ian P. Shaeffer, Eric C. Gaertner, John T Orchard, Michael W. Murphy, Ronald P. Songco, Corey N. Axelowitz, Brett W. Degner
-
Patent number: 11726941Abstract: The present disclosure relates to a modular management gateway apparatus for providing keyboard, video and mouse communications with a target device in communication with the apparatus. The apparatus may have a housing with a field programmable gate array (FPGA) housed within the housing. An uplink port is included to enable communication between a user operated device and the apparatus via a network. A memory is used for containing a software module for carrying out at least one operating feature of the apparatus. A video compression hardware and software subsystem is used for providing 4K video transfer between the apparatus and the target device. A USB-C enables video signals and serial data to be communicated between the apparatus and the target device.Type: GrantFiled: September 15, 2021Date of Patent: August 15, 2023Assignee: VERTIV IT SYSTEMS, INC.Inventors: Joerg Weedermann, Haralson K. Reeves, Jr., Donald A. Sturgeon, Agustin Roca
-
Patent number: 11720508Abstract: In a method for the emergency shutdown of a bus system, and a bus system, having a master module and bus subscribers disposed in series, the master module and the bus subscribers sending data packets to one another with the aid of a data line, the method has the temporally consecutive method steps: in a first method step, a bus subscriber and/or the master module detect(s) an error status, in a second method step, the bus subscriber and/or the master module send(s) an emergency signal to all bus subscribers and to the master module, in a third method step, a further bus subscriber receives the emergency signal, immediately forwards it to an adjacent bus subscriber and simultaneously evaluates it, and in a fourth method step, the further bus subscriber shuts itself down automatically.Type: GrantFiled: February 15, 2022Date of Patent: August 8, 2023Assignee: SEW-EURODRIVE GMBH & CO. KGInventor: Manuel Fuchs
-
Patent number: 11709791Abstract: In some embodiments, a system is provided for communicating USB information via an extension medium. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The UFP device and the DFP device are communicatively coupled via a non-USB extension medium, and allow a host device communicatively coupled to the UFP device and a USB device communicatively coupled to the DFP device to communicate via USB-compliant techniques. In some embodiments, the DFP device generates synthetic request packets to request additional data packets from the USB device compared to those requested by the host device. In some embodiments, the DFP device is configured to store a request packet in a packet queue if the request packet is received from the UFP device while the DFP device is busy receiving a response to a previous synthetic request packet from the USB device.Type: GrantFiled: September 15, 2021Date of Patent: July 25, 2023Assignee: Icron Technologies CorporationInventor: Mohsen Nahvi
-
Patent number: 11704268Abstract: The present disclosure relates to a USB 2.0 photoelectric transmission system, which includes a first USB 2.0 connector, a second USB 2.0 connector, a first signal directional interpreting circuit, a second signal directional interpreting circuit, a first laser, a second laser, a first photodetector and a second photodetector, wherein a first end and a second end of the first signal directional interpreting circuit are respectively connected with a D+ pin and a D? pin of the first USB 2.0 connector; a third end and a fourth end of the first signal directional interpreting circuit are respectively connected with the first laser and the second photodetector.Type: GrantFiled: December 13, 2021Date of Patent: July 18, 2023Assignee: SHENZHEN AFALIGHT CO., LTD.Inventors: Junbin Huang, Quanfei Fu, Yong Yang, Jihui Chen, Ling Long
-
Patent number: 11704944Abstract: The present application discloses a display panel and a display device. The display panel includes: a common electrode layer including a plurality of columns of first common electrodes, wherein each column of the plurality of columns of the first common electrodes includes a plurality of touch electrodes insulated from each other; and a driving module. Each of the plurality of touch electrodes is electrically connected to the driving module through one or more touch leads. A number of the touch leads corresponding to each of or adjacent ones of the plurality of touch electrodes gradually increases along a direction away from the driving module.Type: GrantFiled: July 17, 2020Date of Patent: July 18, 2023Assignee: AUTEL INTELLIGENT TECHNOLOGY CORP., LTD.Inventors: Weilin Wang, Ye Liao
-
Patent number: 11698877Abstract: Embodiments of the present invention provide a connecting apparatus and a system. The connecting apparatus includes N interconnection units, M line processing units, and X switch processing units, where each interconnection unit is connected to at least one switch processing unit, each switch processing unit is connected to only one interconnection unit, each interconnection unit is connected to the M line processing units, each line processing unit is connected to the N interconnection units, M is a positive integer, N is a positive integer, and X is greater than or equal to N. In addition, the embodiments of the present invention further provide another connecting apparatus and system. According to the foregoing technical solutions, a connecting mode between an LPU and an SPU is relatively flexible.Type: GrantFiled: July 28, 2020Date of Patent: July 11, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Chongyang Wang, Jun Zhang
-
Patent number: 11698870Abstract: The present disclosure includes apparatuses and methods related to a data buffer in a non-volatile dual in-line memory module (NVDIMM). An example apparatus can include a data buffer couplable to a host, a first memory device (e.g., volatile memory), wherein the first memory device is coupled to the data buffer via a first bus, a second memory device (e.g., non-volatile memory), and a controller, wherein the controller is coupled to the data buffer via a second bus and wherein the controller is configured to cause a data transfer from first memory device to the second memory device via the data buffer and the second bus.Type: GrantFiled: January 29, 2021Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventor: William A. Lendvay
-
Patent number: 11693814Abstract: A system and device for expanding accessible memory of a processor is provided. An interposer is coupled to the processor and a memory module. The interposer is coupled to a first connection and a second connection. The interposer includes a memory controller circuit. The memory controller circuit receives signals from the processor, using the first connection, and transmits the received signals to the memory module, using the second connection. The interposer expands memory access without an unnecessary second processor.Type: GrantFiled: December 18, 2020Date of Patent: July 4, 2023Assignee: QUANTA COMPUTER INC.Inventors: Le-Sheng Chou, Sz-Chin Shih
-
Patent number: 11689201Abstract: An aspect relates to an apparatus including a first pair of switching devices configured to selectively couple an application processor to a Universal Serial Bus (USB) differential data transmission lines; a USB host port connector coupled to the USB differential data transmission lines; a second pair of switching devices configured to selectively couple an audio circuit to the USB differential data transmission lines; and an equalizer including differential terminals coupled to the USB differential data transmission lines, respectively.Type: GrantFiled: July 26, 2021Date of Patent: June 27, 2023Assignee: QUALCOMM INCORPORATEDInventors: Vijayakumar Dhanasekaran, Khaled Mahmoud Abdelfattah Aly
-
Patent number: 11689478Abstract: A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the receiving device ignores one or more of the skip data elements. If the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.Type: GrantFiled: May 19, 2020Date of Patent: June 27, 2023Assignee: Achronix Semiconductor CorporationInventors: Naresh Sharma, Mohan Vedam
-
Patent number: 11688981Abstract: A redriver includes a plurality of channels coupled to an interface, a number of detectors coupled to the plurality of channels, and a controller that determines an orientation of the interface based on states detected by the number of detectors. The controller determines that the interface is in a first orientation when a first combination of states is detected for the plurality of channels, and determines that the interface is in a second orientation when a second combination of states is detected for the plurality of channels.Type: GrantFiled: March 6, 2019Date of Patent: June 27, 2023Assignee: NXP B.V.Inventors: Abhijeet Chandrakant Kulkarni, Krishnan Tiruchi Natarajan, Siamak Delshadpour, Ronald Dean Smith, Allen Yu-feng Tung, Hans de Kuyper, Amrita Deshpande, Sivakumar Reddy Papadasu
-
Patent number: 11675730Abstract: A USB module includes a first USB port configured to connect a first USB-compatible device with a first USB cable and a USB plug, and a second port configured to connect a second USB-compatible device with a second USB cable. The USB cables are multi-core and respectively comprise first and second configuration lines. An interface is arranged between the first USB port and the second port in a housing interior of a housing of the USB module. The interface makes at least the first configuration line connectable to the second configuration line. The interface comprises a semiconductor module configured to reference to a ground potential of the USB module at least one output signal at the USB module on a configuration connection between the first and second configuration lines.Type: GrantFiled: October 6, 2021Date of Patent: June 13, 2023Assignee: MD ELEKTRONIK GMBHInventors: Rudolf Engl, Stefan Fuchs, Klaus Bramhofer
-
Patent number: 11675725Abstract: An interposer includes a planar substrate and a pad array formed on a bottom side of the planar substrate to connect with a pin array within a CPU socket. A serial computer expansion bus connector is formed on the top side of the planar substrate and is electronically coupled to a portion of the pad array. The interposer further includes a perimeter structure adapted for securing to a CPU carrier. The interposer may be included in a kit with a heatsink securable to the CPU socket, wherein the heatsink includes a contact area for contacting the interposer and applying a load to the interposer. A printed circuit board assembly may include first and second CPU sockets that are connected by a CPU interconnect, where the interposer may be installed in the first CPU socket and a CPU may be installed in the second CPU socket.Type: GrantFiled: September 29, 2021Date of Patent: June 13, 2023Inventors: Paul T. Artman, Martin W Hiegl, Andrew Junkins
-
Patent number: 11677652Abstract: A port adaptation method applied to a network device including a port adaptation apparatus includes probing whether the first port and the second port are connected to power sourcing equipment, and maintaining or switching one of the first port and the second port that is connected to power sourcing equipment as, or to, a powered state, and a state of the other port as, or to, a powering state.Type: GrantFiled: June 23, 2021Date of Patent: June 13, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Shiyong Fu, Yan Zhuang, Rui Hua
-
Patent number: 11645217Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.Type: GrantFiled: May 25, 2021Date of Patent: May 9, 2023Assignee: Western Digital Technologies, Inc.Inventors: Scott Jinn, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
-
Patent number: 11636811Abstract: The preset disclosure provides a data burning method and a data burning device. The data burning method comprises receiving a differential signal data packet, which is transmitted by a signal generator, by a driver IC through a differential signal interface, the differential signal data packet including grayscale data; parsing the differential signal data packet by the driver IC to obtain the grayscale data; and burning the grayscale data to a memory by the driver IC.Type: GrantFiled: August 30, 2018Date of Patent: April 25, 2023Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Guoqiang Wu, Chuanyan Lan, Yong Yu, Taehyun Kim, Lianbin Liu
-
Patent number: 11636060Abstract: An electronic device includes a connector (e.g., a USB connector), a first element configured to operate the connector as a host device connector, a second element configured to operate the connector as a peripheral device connector, and a third element configured to generate a first signal upon connection of the connector. The first signal is indicative of whether the device is to operate as a host device or a peripheral device.Type: GrantFiled: October 20, 2020Date of Patent: April 25, 2023Assignee: STMICROELECTRONICS (GRAND OUEST) SASInventor: Amelie Delaunay
-
Patent number: 11630796Abstract: A serial peripheral interface (SPI) communication system includes a memory configured with a start register address and an end register address that define a register address range for a data operation; a chip select terminal configured to receive a chip select signal comprising an active and idle signal levels that define a plurality of chip select frames; a serial data input terminal configured to receive a master out, slave in (MOSI) signal, wherein the MOSI signal includes configuration information received in a first chip select frame of the data operation, wherein the configuration information includes an operation command bit indicating whether the data operation is a write operation or a read out operation and an auto-incrementation control bit indicating whether automatic register address incrementation across chip select frames is enabled or disabled; and a serial data output terminal configured to transmit a master in, slave out (MISO) signal.Type: GrantFiled: May 7, 2021Date of Patent: April 18, 2023Assignee: Infineon Technologies AGInventors: Andreas Jansen, Richard Heinz, Catalina-Petruta Juglan, Stephan Leisenheimer, Lacramioara Mihaela Smochina