Abstract: The invention relates to an auxiliary instrument for insertion into vessels or lumens with small inner diameters. The auxiliary instrument has a proximal end and a distal end and has at least one localization element whose position and orientation can be determined with an electromagnetic position detection system. The localization element is located directly adjacent to or at least close to the distal end of the auxiliary instrument and is configured to capture an alternating electromagnetic field. A distal end region of the auxiliary instrument extends from the distal end of the auxiliary instrument to a proximal end of the localization element such that the localization element is located within the distal end region. In that part of the distal end region in which the localization element is located, the auxiliary instrument has a low bending stiffness of less than 10 Nmm2, at least in sections.

Abstract: A sense amplifier includes a first switch unit, a second switch unit, and an amplifier-latch module. A first port of the amplifier-latch module is electrically connected, via the first switch unit, to a bit line connected with a storage unit, and a second port of the amplifier-latch module is electrically connected to a reference voltage signal via the second switch unit. The amplifier-latch module is configured to amplify a signal in a sensing amplification phase. The first switch unit is configured to transmit a voltage on the bit line to the first port before the sensing amplification phase. The second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification phase, and disconnect an electrical connection between the reference voltage signal and the second port in the sensing amplification phase.

Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.

Abstract: A method of operating a memory circuit includes enabling a first row of select transistors, disabling a second row of select transistors, enabling a first row of memory cells in response to a first word line signal, and disabling a second row of memory cells in response to a second word line signal. Enabling the first row of select transistors includes turning on a first select transistor in the first row of select transistors in response to a first select line signal thereby electrically coupling a first local bit line and a global bit line to each other. Disabling the second row of select transistors includes turning off a second select transistor in the second row of select transistors in response to a second select line signal thereby electrically decoupling a second local bit line and the global bit line from each other.

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Abstract: According to one embodiment, a memory device includes: first and second stacks each including a first semiconductor layers arranged in a first direction perpendicular to a surface of a substrate, the first and second stacks arranged in a second direction parallel to the surface of the substrate; a second semiconductor layer above the first stack in the first direction; a third semiconductor layer above the second stack in the first direction; memory cells between the first semiconductor layers and the word lines; a first transistor on the second semiconductor layer; and a second transistor on the third semiconductor layer. The first and second stacks are arranged at a first pitch, the first and second semiconductor layers are arranged at a second pitch equal to the first pitch.

Abstract: A switching power supply module and a memory storage device are disclosed. The switching power supply module includes a first voltage regulation circuit, a second voltage regulation circuit, a switch circuit and a control circuit. The first voltage regulation circuit is configured to regulate an original power as a first power. The second voltage regulation circuit is configured to regulate the original power as a second power. The control circuit is configured to control the switch circuit to conduct a first power supply path under a first status to provide the first power to the first power supply target. The control circuit is further configured to control the switch circuit to conduct a second power supply path under a second status to provide the second power to the second power supply target.

Abstract: According to one embodiment, a memory device includes: a memory cell including a memory element and a switching element; and a circuit that applies a first write pulse having a first polarity to the memory cell at the time of writing first data in the memory cell and applies a second write pulse having a second polarity different from the first polarity to the memory cell at the time of writing second data in the memory cell. The switching element has polarity dependence according to the first and second polarities.

Abstract: An integrated circuit includes first and second arrays of resistors, and a plurality of interface circuits. Each resistor in the first array is electrically coupled between a corresponding first input conductive line among a plurality of first or second input conductive lines, and a corresponding first output conductive line among a plurality of first or second output conductive lines. Each resistor in the second array is electrically coupled between a corresponding second input conductive line among a plurality of second input conductive lines, and a corresponding second output conductive line among a plurality of second output conductive lines. Each interface circuit is electrically coupled between a corresponding first output conductive line and a corresponding second input conductive line. Each interface circuit is configured to receive a signal on the corresponding first output conductive line, and apply an analog voltage corresponding to the signal to the corresponding second input conductive line.

Abstract: Methods and systems for providing feedback during a medical procedure. The 3D position and orientation of a tracked tool are determined, relative to a site of the medical procedure, based on tracking information received from a tracking system. The 3D position and orientation are mapped to a common coordinate space, to determine the 3D position and orientation relative to a field-of-view (FOV) of an optical camera that is capturing an optical image of the site. Navigational information associated with the 3D position and orientation is determined. A virtual representation of the navigational information overlaid on the FOV and displayed. The displayed virtual representation is updated when the 3D position and orientation of the tracked tool changes or when the FOV changes, in accordance with the change.

Abstract: A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Abstract: A word line driving circuit includes a first circuit and a second circuit. The first circuit is configured to provide a first word line driving voltage and a second word line driving voltage based on a first control signal, a second control signal, a first bias voltage, a second bias voltage and a base voltage. The second circuit is configured to provide the first control signal and the second control signal based on a third control signal, a fourth control signal, a word line control signal, a reverse word line control signal, the first bias voltage, the second bias voltage and the base voltage. The first bias voltage and the second bias voltage have different levels during the read mode and the program mode for adaptively adjusting the read voltage and the program voltage, thereby improving the data access time.

Abstract: Various approaches to focusing an ultrasound transducer includes causing the ultrasound transducer to transmit ultrasound waves to the target region; causing the detection system to indirectly measure the focusing properties; and based at least in part on the indirectly measured focusing properties, adjusting a parameter value associated with at least one of the transducer elements so as to achieve a target treatment power at the target region.

Abstract: Systems and devices are provided for generating focused ultrasound pulses based on a transducer assembly having a piezoelectric layer coupled to an acoustic lens. In some example embodiments, the piezoelectric layer is a composite piezoelectric material having an acoustic impedance configured to match the acoustic impedance of the acoustic lens. The acoustic lens may be formed from aluminum, or an alloy thereof, and may have a distal surface having a non-spherical profile for producing a focal region that is smaller than an equivalent spherical lens. The acoustic lens may have an f-number less than unity. In some embodiments, the acoustic lens is coated with a polymer acoustic impedance matching layer that is compatible with deposition via chemical vapor deposition, such as a p-xylylene based polymer. In some embodiments, the acoustic lens is formed from aluminum or an alloy thereof, and the polymer acoustic impedance matching layer is a Parylene layer.

Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Abstract: The storage device includes a non-volatile memory with control circuitry and an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops which include applying a programming pulse to a selected word line to program at least one memory cell of the selected word line to a programmed data state. The programming loops also include simultaneously applying a verify pulse to the selected word line to verify a data state being programmed, applying a first voltage to at least one unselected word line that has not been programmed, and applying a second voltage to at least one unselected word line that has already been programmed. The first voltage is determined as a function of the programmed data state to reduce a voltage threshold distribution across the memory cells.

Abstract: A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.