Abstract: An amplifier having orthogonal tuning elements is provided. In one embodiment, an amplifier comprises an input amplifier stage having a first tuning element used to control a first performance criteria of the amplifier; an output amplifier stage operatively coupled to the first amplifier stage; a bias circuit operatively coupled to the second amplifier stage and having a second tuning element used to control a second performance criteria of the amplifier; and wherein the first tuning element operates substantially independent of the second tuning element.

Abstract: Techniques for dynamically generating a headroom voltage for an envelope tracking system. In an aspect, an initial headroom voltage is updated when a signal from a power amplifier (PA) indicates that the PA headroom is insufficient. The initial headroom voltage may be updated to an operating headroom voltage that includes the initial voltage plus a deficiency voltage plus a margin. In this manner, the operating headroom voltage may be dynamically selected to minimize power consumption while still ensuring that the PA is linear. In a further aspect, a specific exemplary embodiment of a headroom voltage generator using a counter is described.

Abstract: A high-frequency amplifier circuit (10) includes a high-frequency amplifier (101) and a bias circuit (20). The bias circuit (20) includes bias control elements (102, 103). An emitter of the bias control element (102) is connected to a base of the amplifier (101) via a resistor (201). An emitter of the bias control element (103) is connected to a collector of a switch element (104) via a resistor (203). The switch element (104) is a common emitter. A resistor (204) is connected between the emitter of the bias control element (102) and the emitter of the bias control element (103). A control voltage (VCTL) is applied to bases of the bias control elements (102, 103). A bias current adjustment voltage (VLIN) corresponding to an operation mode is applied to a base of the switch element (104).

Abstract: Multimode radio frequency (RF) amplifier systems and techniques are disclosed. In one embodiment, a multimode radio frequency (RF) amplifier system has a first RF amplifier and a second RF amplifier. The first RF amplifier may support a first RF communication standard. The second RF amplifier may support a second RF communication standard. The first RF amplifier includes an auxiliary circuit. The auxiliary circuit may provide a service or a utility to a second RF amplifier. For example, the auxiliary circuit may generate a supply voltage to power the second RF amplifier.

Abstract: A signal amplifier may include a first common gate-type amplifying unit connected to a source voltage terminal, dividing an input signal into two signals, amplifying the two divided signals, respectively, and providing a first signal and a second signal, a second common gate-type amplifying unit connected to a ground, dividing the input signal into two signals, amplifying the two divided signals, respectively, and providing a third signal and a fourth signal, a signal summing unit summing the first signal and the second signal from the first common gate-type amplifying unit and the third signal and the fourth signal from the second common gate-type amplifying unit, and an impedance matching unit impedance-matching a signal summed by the signal summing unit.

Abstract: The invention relates to a Doherty amplifier for amplifying an input signal at an operating frequency, comprising: a main amplifier; a first peak amplifier; a second peak amplifier, each of the amplifiers comprising an input for receiving the input signal and an output for providing an amplified signal, a plurality of peak amplifiers, each of the amplifiers comprising an input for receiving the input signal and an output for providing an amplified signal; a first input phase shifter; a second input phase shifter; a first capacitor coupled between the source and drain of the first peak amplifier; a first output phase shifter and a second output phase shifter.

Abstract: Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.

Abstract: A three-way sequential power amplifier includes an input network connected to a main amplifier, a first peak amplifier, a second peak amplifier, which in turn are connected to a three-way output network. An input signal for an input port of the input network is a wideband radio frequency (RF) signal with a time varying amplitude. An output port of the output network can be connected to an antenna, via a bandpass filter, to attenuate out of band frequencies.

Abstract: A Doherty amplifier has different drain voltages applied to the power transistors of the main and peaking stages. The impedance inverter comprises at least one first series phase shifting element between the output of the main amplifier and the Doherty amplifier output and at least one second series phase shifting element between the output of the peaking amplifier and the Doherty amplifier output. This provides a wideband combiner. The combination of this wideband combiner and different drain drive levels provides an improved combination of efficiency and bandwidth.

Abstract: Embodiments of apparatuses and systems for a bias network providing accurate quiescent current control are generally described herein. Other embodiments may be described and claimed.

Abstract: A reconfigurable load modulation amplifier having a carrier amplifier and a peak amplifier that are coupled in parallel is disclosed. The peak amplifier provides additional power amplification when the carrier amplifier is driven into saturation. A quadrature coupler coupled between the carrier amplifier and the peak amplifier is configured to combine power from both the carrier amplifier and the peak amplifier for output through an output load terminal. The reconfigurable load modulation amplifier further includes control circuitry coupled to an isolation port of the quadrature coupler and configured to provide adjustable impedance at the isolation port of the quadrature coupler. As such, impedance at the isolation port of the quadrature coupler is tunable such that at least a carrier or peak amplifier is presented with a quadrature coupler load impedance that ranges from around about half an output load termination impedance to around about twice the output load termination impedance.

Abstract: A circuit and technique are provided to control bias setting to an FET based common source RF amplifier that can operate with large signals present. The circuit and technique described herein use a second FET in an identical circuit having the gate circuits connected in parallel and being sourced by the same drain voltage that serves as a reference to a first circuit bias setting. The drain current in a first FET will include both the bias and RF amplification current, whereas the second FET only carries the bias current. Because the devices and circuits are matched, the gate voltage variations will appear in both FETs thereby providing regulation of the drain current.

Abstract: A tracking power supply for one or more amplifiers includes one or more cascaded sets of power boost circuits to temporarily boost the positive and/or negative power supply rail, respectively. Each power boost circuit may include a gain element and an energy source such as a capacitor or battery, and the power boost circuits are linked to provide a greater degree of voltage boost when needed. An optional control circuit monitors amplifier output signal levels, or separately amplified input signal levels, and provides power boost control signals to the power boost circuits, which temporarily raise or lower the positive and/or negative supply voltages above or below the nominal voltage rails in tandem with the highest and lowest output signals, respectively, from the amplifier(s).

Abstract: An apparatus, which includes a first electronic device, a first nonlinear capacitance compensation circuit, and a capacitance compensation control circuit, is disclosed. The first electronic device has a first nonlinear capacitance and is coupled to the first nonlinear capacitance compensation circuit, which has a first compensation capacitance and receives a first compensation control signal. The capacitance compensation control circuit adjusts the first compensation capacitance using the first compensation control signal to at least partially linearize the first nonlinear capacitance.

Abstract: A system and method for adjusting a common mode output voltage in an instrumentation amplifier is provided. In one aspect, the common mode output voltage is increased or decreased with respect to the common mode input voltage to enable high amplification of the signal input to the instrumentation amplifier. Moreover, the common mode output voltage can be driven to (or approximately to) a target voltage value such as, but not limited to, half the supply, even if the common mode input voltage is close to supply or ground rail voltage. Thus, a high amplification of the differential input voltage can be obtained and utilized for various applications requiring rail to rail input.

Abstract: Improved linearity performance for multi-mode power amplifiers. A power amplifier (PA) assembly can include a radio-frequency (RF) amplification path having a first stage and a second stage, with each stage including a transistor. The PA assembly can further include a biasing circuit having a first bias path between a supply node and the base of a corresponding transistor. The PA assembly can further include a linearizing circuit implemented as either or both of a second bias path and a coupling path relative to the first bias path. The second bias path can be configured to provide an additional base bias current to the base under a selected condition. The coupling path can be configured to improve linearity of the corresponding transistor operating in a first mode while allowing a ballast resistance to be sufficiently robust for the corresponding transistor operating in a second mode.

Abstract: A power amplifying apparatus is provided. The power amplifying apparatus includes a first substrate and N power amplifiers. The N power amplifiers are disposed on the first substrate, the power amplifiers respectively receives N input signals, wherein frequency bands of at least two of the inputs signals are different. And the power amplifiers respectively generate M output signals, wherein the N is a positive integer greater than 2, and M is a positive integer not equal to N.

Abstract: An amplification device includes: a first circuit configured to: split an input signal into a first signal and a second signal, and adjust the first signal so that an amplitude of the first signal is less than an amplitude of the second signal by a reduced value, a first amplifier configured to amplify the adjusted first signal, a second amplifier configured to amplify the second signal, and a second circuit configured to: determine a reflection coefficient in case where the amplified second signal is a travelling wave and the amplified first signal is a reflected wave, and determine the reduced value based on the reflection coefficient.

Abstract: In some embodiments, a source follower circuit may include a first level shifter configured to receive an input voltage; an N-type Metal-Oxide-Semiconductor (NMOS) transistor having a gate terminal coupled to an output of the first level shifter; a second level shifter configured to receive the input voltage; a P-type Metal-Oxide-Semiconductor (PMOS) transistor having a gate terminal coupled to an output of the second level shifter and a source terminal coupled to a source terminal of the NMOS transistor; and an amplifier configured to receive the input voltage and to output a current at a node between the source terminal of the NMOS transistor and the source terminal of the PMOS transistor, wherein the current is determined based upon a difference between the input voltage and a reference voltage.

Abstract: Multi-mode power amplifiers (PAs) having improved linearity. A PA can include an amplifying bipolar junction transistor (BJT) configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a biasing circuit configured to provide a first bias signal or a second bias signal to the BJT for operation in a first mode or a second mode. Each of the first bias signal and the second bias signal can be routed to the BJT through a path that includes a common node and a ballast. The PA can further include a linearizing circuit implemented between the common node and a node along an input path for the BJT. The linearizing circuit can be configured as a coupling path to improve linearity of the PA operating in the first mode while allowing the ballast to be sufficiently robust for the PA operating in the second mode.