Abstract: An amplifier system may include a first feedback loop coupled between an output of an amplifier to an input of a modulator for regulating an output voltage driven at the output of the amplifier to a first terminal of a load of the amplifier system, a sense resistor for sensing a physical quantity associated with the amplifier, a second control loop coupled to the sense resistor such that the sense resistor is outside of the second control loop, the second control loop configured to regulate a common-mode voltage at a second terminal of the load, and a common-mode feedforward circuit coupled to the sense resistor and configured to minimize effects of a signal-dependent common-mode feedback of the sense resistor.

Abstract: Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network coupled to a gate of a cascode FET transistor of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first and/or the second networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across stacked FET transistors of the amplifier.

Abstract: Apparatuses include (among other components) a first gain device connected to receive an initial voltage, a second gain device in series with the first gain device and connected to receive output of the first gain device, differential gain devices connected to receive outputs from the first gain device and the second gain device (the differential gain devices provide opposite voltage outputs from the apparatus) and high-frequency compensation feed-forward paths connected to the first gain device and the second gain device.

Abstract: A low-cost, small-size Wilkinson-type combiner that suppresses the risk of damaging an isolation resistor due to combination loss is provided. The combiner comprises first and second input terminals to which RF signals are input; an output terminal; a wiring line that combines the RF signals input to the first and second input terminals, and outputs the combined signal to the output terminal; an isolation unit provided between the first and second input terminals and formed by a first isolation resistor, a transformer, and a second isolation resistor connected in series; a detection circuit connected to a secondary coil of the transformer and configured to detect a current flowing in the secondary coil; and a determination circuit that outputs a control signal to block input of RF signals to the first and second input terminals if the current flowing in the isolation unit and detected by the detection circuit is higher than or equal to a prescribed value.

Abstract: A balun configured for a power range between 500 W and 5 kW output includes a balanced signal port comprising a first connection and a second connection and further includes a single-ended signal port comprising a third connection and a fourth connection, the fourth connection being connected to ground. In addition, the balun includes a first capacitor disposed between the first connection and a first end of a first resistor and a second capacitor disposed between the second connection and the first end of the first resistor. A second end of the first resistor is connected to ground.

Abstract: A bandpass parametric amplifier circuit includes a plurality of unit cells. At least one unit cell includes a first inductor having a first node coupled to a center conductor and a second node coupled to ground. There is a first capacitor having a first node coupled to the center conductor and a second node coupled to ground. There is a second inductor having a first node coupled to the center conductor. A second capacitor has a first node coupled to a second node of the second inductor. The second capacitor and the second inductor are in series with the center conductor.

Abstract: A power amplifier includes a power switching circuit, a driver circuit, and an amplifier circuit. The power switching circuit is configured to receive a first voltage and a second voltage, and provide the first voltage or the second voltage according to an operation mode of the power amplifier. The driver circuit is coupled to the power switching circuit. The driver circuit is configured to operate according to the first voltage or the second voltage and generate a driving signal according to an input signal. The amplifier circuit is coupled to the power switching circuit and the driver circuit. The amplifier circuit is configured to operate according to the first voltage or the second voltage and generate an output signal according to the driving signal.

Abstract: A circuit comprises an amplifier network including a first amplifier and a second amplifier and a first transistor having a first base. The first transistor is thermally isolated from the second amplifier. The circuit further comprises a second transistor having a second base. The second transistor is thermally linked to the second amplifier. The circuit further comprises coupling circuitry configured to couple the first base to the second base.

Abstract: An error amplifier includes an output pin coupled to a pulse width modulation (PWM) comparator of a buck-boost converter. A first transconductance amplifier adjusts an output current at the output pin and operates in a constant voltage mode. The first transconductance amplifier includes a first positive input to receive a first voltage reference and a first negative input coupled to a tap point of a voltage divider coupled between a voltage bus and a ground of the buck-boost converter. A second transconductance amplifier also adjusts the output current at the output pin and operates in a constant current mode. The second transconductance amplifier includes a second positive input to receive a second voltage reference and a second negative input coupled to a current sense amplifier, the current sense amplifier being coupled to a sense resistor positioned inline along the voltage bus.

Abstract: Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

Abstract: This invention relates to a self-excited oscillation suppression device and method for the power amplifying circuit, belonging to the field of electronic technology. Said power amplifying circuit includes a FET and a feedback loop. Said device includes: a first compensation circuit which is connected between a drain and a gate of the FET and a second compensation circuit which is connected in parallel with a feedback resistor of said feedback loop. It can solve self-excited oscillation caused by deep negative feedback in the existing power amplifying circuit. The first compensation circuit can shift the open-loop gain curve forward as a whole, and the second compensation circuit can speed up the closure of the feedback gain curve and the open-loop gain curve so that the two curves will close up before the self-excited oscillation; the self-excited oscillation will be suppressed, and the stability of the power amplifying circuit will be improved.

Abstract: An amplifier circuit is provided. The amplifier circuit outputs a pair of differential output signals through a first output terminal and a second output terminal. The amplifier circuit includes a first amplifier stage electrically connected to a first node and a second node for amplifying a pair of differential input signals; a second amplifier stage which is electrically connected to the first node and the second node and coupled to the first output terminal and the second output terminal; a first switch, coupled between the first output terminal and a first reference voltage; a second switch, coupled between the second output terminal and the first reference voltage; a third switch, coupled between the first node and the first reference voltage; a fourth switch coupled between the second node and the first reference voltage; and a fifth switch coupled between a second reference voltage and the first amplifier stage.

Abstract: An output stage of an operational amplifier includes a low voltage (LV) metal oxide semiconductor (MOS) device and a dynamic current limit circuit. An output current of the operational amplifier flows through the LV MOS device. The dynamic current limit circuit is configured to sense a drain voltage of the LV MOS device and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.

Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.

Abstract: Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require IDD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit.

Abstract: This application relates to amplifier circuitry, in particular class-D amplifiers, operable in open-loop and closed-loop modes. An amplifier (300) has a forward signal path for receiving an input signal (SIN) and outputting an output signal (SOUT) and a feedback path operable to provide a feedback signal (SFB) from the output. A feedforward path provide a feedforward signal (SFF) from the input and a combiner (105) is operable to determine an error signal (?) based on a difference between the feedback signal and the feedforward signal. The feedforward comprises a compensation module (201) configured to apply a controlled transfer function to the feedforward signal in the closed-loop mode of operation, such that an overall transfer function for the amplifier is substantially the same in the closed-loop mode of operation and the open-loop mode of operation.

Abstract: An enhanced current mirror can be utilized to accurately control a bias current associated with an amplifier. A current controller component (CCC) can employ the enhanced current mirror and can be associated with the amplifier. The CCC can comprise a comparator that can compare an adjusted supply voltage level to a reference voltage level, the adjusted supply voltage level relating to a supply voltage level of a supply voltage supplied to the amplifier and CCC. The CCC can control switching of an operational state of a transistor of the comparator to switch in or out a resistance of a reference resistor component associated with the supply voltage, based on a result of the comparison of the adjusted supply voltage level to the reference voltage level, to facilitate accurately controlling an amount of bias current associated with the amplifier. The CCC and amplifier can be situated on the same die.

Abstract: Embodiments of the present disclosure provide a chopper amplifier circuit that includes an operational amplifier, and a notch filter to be operated by a chopping pulse. The notch filter has a first branch that has a first capacitor, and a second branch that has a second capacitor. A chopping delay switch is connected to the first branch and the second branch of the notch filter. A control circuit is to close the chopping delay switch to short-circuit the first branch and the second branch of the notch filter to each other. The control circuit is to detect establishment of feedback signal at the chopper amplifier. The control circuit is to open the chopping delay switch, responsive to detecting establishment of the feedback signal at the chopper amplifier.

Abstract: An adaptive DC-DC boost converter arrangement and an electronic circuit including such an arrangement are provided. The arrangement includes a circuit board with a plurality of electronic components mounted thereon, implementing an adaptive DC-DC boost converter circuit and a boost decoupling capacitor. The adaptive DC-DC boost converter circuit comprises a DC-DC boost converter having a converter set value input, a boost supply input, and a boost voltage output, and an adaptive DC-DC boost control unit having a control input and a control output. An acoustical noise suppression filter is present having a filter input connected to the control output of the adaptive DC-DC boost control unit and a filter output connected to the converter set value input of the DC-DC boost converter.

Abstract: An amplifier circuit, which has a first output terminal and a second output terminal, includes a first charge-steering amplifier, a second charge-steering amplifier, a first switch, and a second switch. The first charge-steering amplifier includes a first input terminal, a second input terminal, a first capacitor, and a second capacitor, and is used for amplifying a first input signal in a first operation period. The second charge-steering amplifier includes a third input terminal, a fourth input terminal, the first capacitor, and the second capacitor, and is used for amplifying a second input signal in a second operation period. The first capacitor and the second capacitor charge during the first operation period and discharge during the second operation period.