Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.

Abstract: A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.

Abstract: Memory assemblies include memory chips having chip bond pads on both sides of the memory chip shorted to each other by a single lead of a leadframe. The memory chips contain memory devices arranged to be mounted in a memory package with the major axis of the memory chip aligned substantially parallel with the major axis of its memory package. Memory chips include a first power input chip bond pad in each of at least three quadrants of the memory chip. Memory chips include a second power input chip bond pad in each of at least three quadrants of the memory chip. The chip bond pads are interposed between memory banks of the memory device and the sides of the memory chip containing the memory device. Memory chips of various embodiments contain memory devices having banks of non-volatile flash memory cells whose access commands are synchronized to a system clock.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions of a second conductivity which are formed to extend from the surface of the semiconductor substrate toward the inside thereof in such as manner as to sandwich the first well region therebetween, and a third well region of the second conductivity type which is formed under each of the first well region and the pair of second well regions in the semiconductor substrate. The third well region electrically connects the pair of second well regions to each other. The first well region has at least a portion thereof connected to the region of the semiconductor substrate in which the third well region is not formed.

Abstract: A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor.

Abstract: A semiconductor device having a molded sealing resin for sealing a semiconductor chip on a circuit board thereof reduces resin burrs resulting from the leakage of the sealing resin, and also restrains the occurrence of disconnection caused by a wiring layer being crushed. In the semiconductor device, the sealing resin for sealing the semiconductor chip is molded on the circuit board that has a plurality of wiring patterns and a solder resist for insulatively covering the wiring patterns formed on the front surface thereof, the interval of the wiring patterns is set to range from 50% to 200% of its adjacent interval in a molding line area of the sealing resin.

Abstract: A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.

Abstract: A surface mount chip package comprises a package housing made of a prescribed resin, which is formed to cover a semiconductor chip while avoiding a plurality of conductors extending from the semiconductor chip. A plurality of solder balls are arranged in the package housing in correspondence with a main surface of the semiconductor chip having an integrated circuit and are interconnected with the conductors respectively. An index serving as a marking member is arranged together with the solder balls so as to bring a directivity realized by the shape thereof when viewed in the thickness direction of the semiconductor chip. This allows a user to easily recognize the inclination and position of the package housing without using the solder balls in view of the index, thus establishing a prescribed positioning for an electrical test such as a probing test.

Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.

Abstract: A semiconductor substrate having a first substrate surface which includes a device area in which semiconductor devices are formed and a substrate peripheral portion which does not overlap with the device area. A concavo-convex portion is formed in the substrate peripheral portion. Preferably, a concavo-convex portion is formed in a side portion which adjoins the peripheral portion. The concavo-convex portion formed in the substrate peripheral portion or the side portion may be formed by a method such as dry etching, wet etching, mechanical grinding, electrolytic plating, nonelectrolytic plating, or patterning using one of a resin material and a metal material. A thin processing method includes forming the device area; forming the concavo-convex portion in the substrate peripheral portion; adhering the first substrate surface to a support; and grinding a second substrate surface of the semiconductor substrate, which is opposite with the first substrate surface.

Abstract: To provide a semiconductor device that enables high integration degree, and a manufacturing method therefor. A multi-chip module according to an embodiment of the present invention includes: a first semiconductor chip having a first bonding pad; a second semiconductor chip having a second bonding pad thinner than the first bonding pad; and a bonding wire connected with each of the first bonding pad and the second bonding pad, the first bonding pad being connected with a first bond side end portion of the bonding wire and the second bonding pad being connected with a second bond side end portion of the bonding wire.

Abstract: A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.

Abstract: A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

Abstract: A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film without the SAC structure is etched off except where bit line is formed. A direct nitride film is formed on the entire top and side surface of the bit line so as to cover the bit line in one processing step. Since the upper and side nitride film thicknesses are substantially the same, the height of the bit line can be reduced, enabling further miniaturization. In addition, since the sidewall nitride film is formed without an etch back process, it can more easily be formed with a constant film thickness.

Abstract: A semiconductor device comprises an island shaped channel layer formed on a substrate, the channel later being composed of a semiconductor material, a gate insulation film formed on the channel layer, a gate electrode formed on the gate insulation film, an insulation film formed on both side faces opposite to one direction of the channel layer, a source electrode and a drain electrode made of a metal material and formed on a side face of the insulation layer.

Abstract: A semiconductor device comprises a substrate, a ferroelectric capacitor which includes a ferroelectric film on the substrate, and a stress application layer which applies tensile or compressive stress to the ferroelectric film of the ferroelectric capacitor by applying stress to the substrate.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

Abstract: An image sensor cell includes a first MOS transistor coupled to an operating voltage for providing an output voltage of the image sensor cell with the output voltage changing conformingly with a voltage on a gate of the first MOS transistor. A photodiode is coupled to a floating node which further controls the voltage of the gate of the first MOS transistor. A photoconductor is coupled between the operating voltage and the floating node. The photoconductor has its resistance varying in response to a magnitude change of an imposed illumination so that the floating node is provided with additional electrical charges conformingly through the photoconductor while the photodiode drains electrical charges, thereby decreasing a voltage reduction rate of the voltage on the gate of the first MOS transistor.